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6#ifndef _DDR3_TRAINING_IP_H_
7#define _DDR3_TRAINING_IP_H_
8
9#include "ddr_topology_def.h"
10
11#define TIP_ENG_LOCK 0x02000000
12#define TIP_TX_DLL_RANGE_MAX 64
13
14#define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2)
15#define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1)
16
17#define INIT_CONTROLLER_MASK_BIT 0x00000001
18#define STATIC_LEVELING_MASK_BIT 0x00000002
19#define SET_LOW_FREQ_MASK_BIT 0x00000004
20#define LOAD_PATTERN_MASK_BIT 0x00000008
21#define SET_MEDIUM_FREQ_MASK_BIT 0x00000010
22#define WRITE_LEVELING_MASK_BIT 0x00000020
23#define LOAD_PATTERN_2_MASK_BIT 0x00000040
24#define READ_LEVELING_MASK_BIT 0x00000080
25#define SW_READ_LEVELING_MASK_BIT 0x00000100
26#define WRITE_LEVELING_SUPP_MASK_BIT 0x00000200
27#define PBS_RX_MASK_BIT 0x00000400
28#define PBS_TX_MASK_BIT 0x00000800
29#define SET_TARGET_FREQ_MASK_BIT 0x00001000
30#define ADJUST_DQS_MASK_BIT 0x00002000
31#define WRITE_LEVELING_TF_MASK_BIT 0x00004000
32#define LOAD_PATTERN_HIGH_MASK_BIT 0x00008000
33#define READ_LEVELING_TF_MASK_BIT 0x00010000
34#define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000
35#define DM_PBS_TX_MASK_BIT 0x00040000
36#define RL_DQS_BURST_MASK_BIT 0x00080000
37#define CENTRALIZATION_RX_MASK_BIT 0x00100000
38#define CENTRALIZATION_TX_MASK_BIT 0x00200000
39#define TX_EMPHASIS_MASK_BIT 0x00400000
40#define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000
41#define VREF_CALIBRATION_MASK_BIT 0x01000000
42#define WRITE_LEVELING_LF_MASK_BIT 0x02000000
43
44
45
46enum hws_result {
47 TEST_FAILED = 0,
48 TEST_SUCCESS = 1,
49 NO_TEST_DONE = 2
50};
51
52enum hws_training_result {
53 RESULT_PER_BIT,
54 RESULT_PER_BYTE
55};
56
57enum auto_tune_stage {
58 INIT_CONTROLLER,
59 STATIC_LEVELING,
60 SET_LOW_FREQ,
61 LOAD_PATTERN,
62 SET_MEDIUM_FREQ,
63 WRITE_LEVELING,
64 LOAD_PATTERN_2,
65 READ_LEVELING,
66 WRITE_LEVELING_SUPP,
67 PBS_RX,
68 PBS_TX,
69 SET_TARGET_FREQ,
70 ADJUST_DQS,
71 WRITE_LEVELING_TF,
72 READ_LEVELING_TF,
73 WRITE_LEVELING_SUPP_TF,
74 DM_PBS_TX,
75 VREF_CALIBRATION,
76 CENTRALIZATION_RX,
77 CENTRALIZATION_TX,
78 TX_EMPHASIS,
79 LOAD_PATTERN_HIGH,
80 PER_BIT_READ_LEVELING_TF,
81 WRITE_LEVELING_LF,
82 MAX_STAGE_LIMIT
83};
84
85enum hws_access_type {
86 ACCESS_TYPE_UNICAST = 0,
87 ACCESS_TYPE_MULTICAST = 1
88};
89
90enum hws_algo_type {
91 ALGO_TYPE_DYNAMIC,
92 ALGO_TYPE_STATIC
93};
94
95struct init_cntr_param {
96 int is_ctrl64_bit;
97 int do_mrs_phy;
98 int init_phy;
99 int msys_init;
100};
101
102struct pattern_info {
103 u8 num_of_phases_tx;
104 u8 tx_burst_size;
105 u8 delay_between_bursts;
106 u8 num_of_phases_rx;
107 u32 start_addr;
108 u8 pattern_len;
109};
110
111struct cs_element {
112 u8 cs_num;
113 u8 num_of_cs;
114};
115
116struct hws_tip_freq_config_info {
117 u8 is_supported;
118 u8 bw_per_freq;
119 u8 rate_per_freq;
120};
121
122struct hws_cs_config_info {
123 u32 cs_reg_value;
124 u32 cs_cbe_value;
125};
126
127struct dfx_access {
128 u8 pipe;
129 u8 client;
130};
131
132struct hws_xsb_info {
133 struct dfx_access *dfx_table;
134};
135
136int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
137int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
138int hws_ddr3_tip_init_controller(u32 dev_num,
139 struct init_cntr_param *init_cntr_prm);
140int hws_ddr3_tip_load_topology_map(u32 dev_num,
141 struct mv_ddr_topology_map *topology);
142int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
143int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
144u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
145u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
146#endif
147
