1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6#ifndef __DDR3_AXP_H 7#define __DDR3_AXP_H 8 9#define MV_78XX0_Z1_REV 0x0 10#define MV_78XX0_A0_REV 0x1 11#define MV_78XX0_B0_REV 0x2 12 13#define SAR_DDR3_FREQ_MASK 0xFE00000 14#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24)) 15 16#define MAX_CS 4 17 18#define MIN_DIMM_ADDR 0x50 19#define FAR_END_DIMM_ADDR 0x50 20#define MAX_DIMM_ADDR 0x60 21 22#ifndef CONFIG_DDR_FIXED_SIZE 23#define SDRAM_CS_SIZE 0xFFFFFFF 24#else 25#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) 26#endif 27#define SDRAM_CS_BASE 0x0 28#define SDRAM_DIMM_SIZE 0x80000000 29 30#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) 31#define CPU_MRVL_ID_OFFSET 0x10 32#define SAR1_CPU_CORE_MASK 0x00000018 33#define SAR1_CPU_CORE_OFFSET 3 34 35/* Only enable ECC if the board selects it */ 36#ifdef CONFIG_BOARD_ECC_SUPPORT 37#define ECC_SUPPORT 38#endif 39#define NEW_FABRIC_TWSI_ADDR 0x4E 40#ifdef CONFIG_DB_784MP_GP 41#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E 42#else 43#define BUS_WIDTH_ECC_TWSI_ADDR 0x4F 44#endif 45#define MV_MAX_DDR3_STATIC_SIZE 50 46#define MV_DDR3_MODES_NUMBER 30 47 48#define RESUME_RL_PATTERNS_ADDR (0xFE0000) 49#define RESUME_RL_PATTERNS_SIZE (0x100) 50#define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + RESUME_RL_PATTERNS_SIZE) 51#define RESUME_TRAINING_VALUES_MAX (0xCD0) 52#define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000) 53#define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000) 54#define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4) 55#define SUSPEND_MAGIC_WORD (0xDEADB002) 56#define REGISTER_LIST_END (0xFFFFFFFF) 57 58/* 59 * Registers offset 60 */ 61 62#define REG_SAMPLE_RESET_LOW_ADDR 0x18230 63#define REG_SAMPLE_RESET_HIGH_ADDR 0x18234 64#define REG_SAMPLE_RESET_CPU_FREQ_OFFS 21 65#define REG_SAMPLE_RESET_CPU_FREQ_MASK 0x00E00000 66#define REG_SAMPLE_RESET_FAB_OFFS 24 67#define REG_SAMPLE_RESET_FAB_MASK 0xF000000 68#define REG_SAMPLE_RESET_TCLK_OFFS 28 69#define REG_SAMPLE_RESET_CPU_ARCH_OFFS 31 70#define REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS 20 71 72/* MISC */ 73/* 74 * In mainline U-Boot we're re-configuring the mvebu base address 75 * register to 0xf1000000. So need to use this value for the DDR 76 * training code as well. 77 */ 78#define INTER_REGS_BASE SOC_REGS_PHY_BASE 79 80/* DDR */ 81#define REG_SDRAM_CONFIG_ADDR 0x1400 82#define REG_SDRAM_CONFIG_MASK 0x9FFFFFFF 83#define REG_SDRAM_CONFIG_RFRS_MASK 0x3FFF 84#define REG_SDRAM_CONFIG_WIDTH_OFFS 15 85#define REG_SDRAM_CONFIG_REGDIMM_OFFS 17 86#define REG_SDRAM_CONFIG_ECC_OFFS 18 87#define REG_SDRAM_CONFIG_IERR_OFFS 19 88#define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28 89#define REG_SDRAM_CONFIG_RSTRD_OFFS 30 90 91#define REG_DUNIT_CTRL_LOW_ADDR 0x1404 92#define REG_DUNIT_CTRL_LOW_2T_OFFS 3 93#define REG_DUNIT_CTRL_LOW_2T_MASK 0x3 94#define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14 95 96#define REG_SDRAM_TIMING_LOW_ADDR 0x1408 97 98#define REG_SDRAM_TIMING_HIGH_ADDR 0x140C 99#define REG_SDRAM_TIMING_H_R2R_OFFS 7 100#define REG_SDRAM_TIMING_H_R2R_MASK 0x3 101#define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9 102#define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3 103#define REG_SDRAM_TIMING_H_W2W_OFFS 11 104#define REG_SDRAM_TIMING_H_W2W_MASK 0x1F 105#define REG_SDRAM_TIMING_H_R2R_H_OFFS 19 106#define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7 107#define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22 108#define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7 109 110#define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410 111#define REG_SDRAM_ADDRESS_SIZE_OFFS 2 112#define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18 113#define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4 114 115#define REG_SDRAM_OPEN_PAGES_ADDR 0x1414 116#define REG_SDRAM_OPERATION_CS_OFFS 8 117 118#define REG_SDRAM_OPERATION_ADDR 0x1418 119#define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24 120#define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20 121#define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xF 122#define REG_SDRAM_OPERATION_CWA_RC_OFFS 16 123#define REG_SDRAM_OPERATION_CWA_RC_MASK 0xF 124#define REG_SDRAM_OPERATION_CMD_MR0 0xF03 125#define REG_SDRAM_OPERATION_CMD_MR1 0xF04 126#define REG_SDRAM_OPERATION_CMD_MR2 0xF08 127#define REG_SDRAM_OPERATION_CMD_MR3 0xF09 128#define REG_SDRAM_OPERATION_CMD_RFRS 0xF02 129#define REG_SDRAM_OPERATION_CMD_CWA 0xF0E 130#define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xF 131#define REG_SDRAM_OPERATION_CMD_MASK 0xF 132#define REG_SDRAM_OPERATION_CS_OFFS 8 133 134#define REG_OUDDR3_TIMING_ADDR 0x142C 135 136#define REG_SDRAM_MODE_ADDR 0x141C 137 138#define REG_SDRAM_EXT_MODE_ADDR 0x1420 139 140#define REG_DDR_CONT_HIGH_ADDR 0x1424 141 142#define REG_ODT_TIME_LOW_ADDR 0x1428 143#define REG_ODT_ON_CTL_RD_OFFS 12 144#define REG_ODT_OFF_CTL_RD_OFFS 16 145#define REG_SDRAM_ERROR_ADDR 0x1454 146#define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474 147#define REG_ODT_TIME_HIGH_ADDR 0x147C 148 149#define REG_SDRAM_INIT_CTRL_ADDR 0x1480 150#define REG_SDRAM_INIT_CTRL_OFFS 0 151#define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2 152#define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3 153 154#define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494 155 156#define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498 157/*#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0xFFFFFF55 */ 158#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0 159#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3 160 161#define REG_DUNIT_ODT_CTRL_ADDR 0x149C 162#define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8 163#define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9 164 165#define REG_DRAM_FIFO_CTRL_ADDR 0x14A0 166 167#define REG_DRAM_AXI_CTRL_ADDR 0x14A8 168#define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0 169 170#define REG_METAL_MASK_ADDR 0x14B0 171#define REG_METAL_MASK_MASK 0xDFFFFFFF 172#define REG_METAL_MASK_RETRY_OFFS 0 173 174#define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14C0 175 176#define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14C4 177#define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8 178#define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14CC 179 180#define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8 181 182#define REG_CS_SIZE_SCRATCH_ADDR 0x1504 183#define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520 184#define REG_DDR_IO_ADDR 0x1524 185#define REG_DDR_IO_CLK_RATIO_OFFS 15 186 187#define REG_DFS_ADDR 0x1528 188#define REG_DFS_DLLNEXTSTATE_OFFS 0 189#define REG_DFS_BLOCK_OFFS 1 190#define REG_DFS_SR_OFFS 2 191#define REG_DFS_ATSR_OFFS 3 192#define REG_DFS_RECONF_OFFS 4 193#define REG_DFS_CL_NEXT_STATE_OFFS 8 194#define REG_DFS_CL_NEXT_STATE_MASK 0xF 195#define REG_DFS_CWL_NEXT_STATE_OFFS 12 196#define REG_DFS_CWL_NEXT_STATE_MASK 0x7 197 198#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538 199#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1F 200#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8 201 202#define REG_READ_DATA_READY_DELAYS_ADDR 0x153C 203#define REG_READ_DATA_READY_DELAYS_MASK 0x1F 204#define REG_READ_DATA_READY_DELAYS_OFFS 8 205 206#define START_BURST_IN_ADDR 1 207 208#define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488 209#define REG_DRAM_TRAINING_ADDR 0x15B0 210#define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0 211#define REG_DRAM_TRAINING_PATTERNS_OFFS 4 212#define REG_DRAM_TRAINING_MED_FREQ_OFFS 2 213#define REG_DRAM_TRAINING_WL_OFFS 3 214#define REG_DRAM_TRAINING_RL_OFFS 6 215#define REG_DRAM_TRAINING_DQS_RX_OFFS 15 216#define REG_DRAM_TRAINING_DQS_TX_OFFS 16 217#define REG_DRAM_TRAINING_CS_OFFS 20 218#define REG_DRAM_TRAINING_RETEST_OFFS 24 219#define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27 220#define REG_DRAM_TRAINING_DFS_REQ_OFFS 29 221#define REG_DRAM_TRAINING_ERROR_OFFS 30 222#define REG_DRAM_TRAINING_AUTO_OFFS 31 223#define REG_DRAM_TRAINING_RETEST_PAR 0x3 224#define REG_DRAM_TRAINING_RETEST_MASK 0xF8FFFFFF 225#define REG_DRAM_TRAINING_CS_MASK 0xFF0FFFFF 226#define REG_DRAM_TRAINING_PATTERNS_MASK 0xFF0F0000 227 228#define REG_DRAM_TRAINING_1_ADDR 0x15B4 229#define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16 230 231#define REG_DRAM_TRAINING_2_ADDR 0x15B8 232#define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17 233#define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4 234#define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3 235#define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2 236#define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1 237#define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0 238 239#define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15BC 240#define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3 241 242#define REG_TRAINING_DEBUG_2_ADDR 0x15C4 243#define REG_TRAINING_DEBUG_2_OFFS 16 244#define REG_TRAINING_DEBUG_2_MASK 0x3 245 246#define REG_TRAINING_DEBUG_3_ADDR 0x15C8 247#define REG_TRAINING_DEBUG_3_OFFS 3 248#define REG_TRAINING_DEBUG_3_MASK 0x7 249 250#define MR_CS_ADDR_OFFS 4 251 252#define REG_DDR3_MR0_ADDR 0x15D0 253#define REG_DDR3_MR0_CS_ADDR 0x1870 254#define REG_DDR3_MR0_CL_MASK 0x74 255#define REG_DDR3_MR0_CL_OFFS 2 256#define REG_DDR3_MR0_CL_HIGH_OFFS 3 257#define CL_MASK 0xF 258 259#define REG_DDR3_MR1_ADDR 0x15D4 260#define REG_DDR3_MR1_CS_ADDR 0x1874 261#define REG_DDR3_MR1_RTT_MASK 0xFFFFFDBB 262#define REG_DDR3_MR1_DLL_ENA_OFFS 0 263#define REG_DDR3_MR1_RTT_DISABLED 0x0 264#define REG_DDR3_MR1_RTT_RZQ2 0x40 265#define REG_DDR3_MR1_RTT_RZQ4 0x2 266#define REG_DDR3_MR1_RTT_RZQ6 0x42 267#define REG_DDR3_MR1_RTT_RZQ8 0x202 268#define REG_DDR3_MR1_RTT_RZQ12 0x4 269#define REG_DDR3_MR1_OUTBUF_WL_MASK 0xFFFFEF7F /* WL-disabled,OB-enabled */ 270#define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12 /* Output Buffer Disabled */ 271#define REG_DDR3_MR1_WL_ENA_OFFS 7 272#define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */ 273#define REG_DDR3_MR1_ODT_MASK 0xFFFFFDBB 274 275#define REG_DDR3_MR2_ADDR 0x15D8 276#define REG_DDR3_MR2_CS_ADDR 0x1878 277#define REG_DDR3_MR2_CWL_OFFS 3 278#define REG_DDR3_MR2_CWL_MASK 0x7 279#define REG_DDR3_MR2_ODT_MASK 0xFFFFF9FF 280#define REG_DDR3_MR3_ADDR 0x15DC 281#define REG_DDR3_MR3_CS_ADDR 0x187C 282 283#define REG_DDR3_RANK_CTRL_ADDR 0x15E0 284#define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xF 285#define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4 286 287#define REG_ZQC_CONF_ADDR 0x15E4 288 289#define REG_DRAM_PHY_CONFIG_ADDR 0x15EC 290#define REG_DRAM_PHY_CONFIG_MASK 0x3FFFFFFF 291 292#define REG_ODPG_CNTRL_ADDR 0x1600 293#define REG_ODPG_CNTRL_OFFS 21 294 295#define REG_PHY_LOCK_MASK_ADDR 0x1670 296#define REG_PHY_LOCK_MASK_MASK 0xFFFFF000 297 298#define REG_PHY_LOCK_STATUS_ADDR 0x1674 299#define REG_PHY_LOCK_STATUS_LOCK_OFFS 9 300#define REG_PHY_LOCK_STATUS_LOCK_MASK 0xFFF 301#define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7FF 302 303#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16A0 304#define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xC0000000 305#define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000 306#define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000 307#define REG_PHY_BC_OFFS 27 308#define REG_PHY_CNTRL_OFFS 26 309#define REG_PHY_CS_OFFS 16 310#define REG_PHY_DQS_REF_DLY_OFFS 10 311#define REG_PHY_PHASE_OFFS 8 312#define REG_PHY_PUP_OFFS 22 313 314#define REG_TRAINING_WL_ADDR 0x16AC 315#define REG_TRAINING_WL_CS_MASK 0xFFFFFFFC 316#define REG_TRAINING_WL_UPD_OFFS 2 317#define REG_TRAINING_WL_CS_DONE_OFFS 3 318#define REG_TRAINING_WL_RATIO_MASK 0xFFFFFF0F 319#define REG_TRAINING_WL_1TO1 0x50 320#define REG_TRAINING_WL_2TO1 0x10 321#define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000 322#define REG_TRAINING_WL_RESULTS_MASK 0x000001FF 323#define REG_TRAINING_WL_RESULTS_OFFS 20 324 325#define REG_REGISTERED_DRAM_CTRL_ADDR 0x16D0 326#define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15 327#define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3F 328/* DLB*/ 329#define REG_STATIC_DRAM_DLB_CONTROL 0x1700 330#define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704 331#define DLB_AGING_REGISTER 0x1708 332#define DLB_EVICTION_CONTROL_REG 0x170c 333#define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710 334 335#define DLB_ENABLE 0x1 336#define DLB_WRITE_COALESING (0x1 << 2) 337#define DLB_AXI_PREFETCH_EN (0x1 << 3) 338#define DLB_MBUS_PREFETCH_EN (0x1 << 4) 339#define PREFETCH_NLNSZTR (0x1 << 6) 340 341/* CPU */ 342#define REG_BOOTROM_ROUTINE_ADDR 0x182D0 343#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12 344 345#define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488 346#define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16 347#define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200FF 348#define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488 349 350#define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700 351 352#define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704 353#define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708 354 355#define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870C 356#define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xFFFFC0FF 357#define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8 358 359#define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710 360 361#define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718 362#define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8 363 364#define REG_CPU_PLL_CTRL_0_ADDR 0x1871C 365#define REG_CPU_PLL_STATUS_0_ADDR 0x18724 366#define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740 367#define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744 368#define REG_DDRPHY_APLL_CTRL_ADDR 0x18780 369 370#define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784 371 372#define REG_SFABRIC_CLK_CTRL_ADDR 0x20858 373#define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8 374 375/* DRAM Windows */ 376#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8 377#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040 378#define REG_XBAR_WIN_4_BASE_ADDR 0x20044 379#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048 380#define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184 381#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078 382 383/* SRAM */ 384#define REG_CDI_CONFIG_ADDR 0x20220 385#define REG_SRAM_WINDOW_0_ADDR 0x20240 386#define REG_SRAM_WINDOW_0_ENA_OFFS 0 387#define REG_SRAM_WINDOW_1_ADDR 0x20244 388#define REG_SRAM_L2_ENA_ADDR 0x8500 389#define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87BC 390 391/* PMU */ 392#define REG_PMU_I_F_CTRL_ADDR 0x1C090 393#define REG_PMU_DUNIT_BLK_OFFS 16 394#define REG_PMU_DUNIT_RFRS_OFFS 20 395#define REG_PMU_DUNIT_ACK_OFFS 24 396 397/* MBUS*/ 398#define MBUS_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x420) 399#define FABRIC_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x424) 400#define MBUS_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x428) 401#define FABRIC_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x42c) 402 403#define REG_PM_STAT_MASK_ADDR 0x2210C 404#define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16 405 406#define REG_PM_EVENT_STAT_MASK_ADDR 0x22120 407#define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17 408 409#define REG_PM_CTRL_CONFIG_ADDR 0x22104 410#define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18 411 412#define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218C4 413#define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18 414 415/* Controller revision info */ 416#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 417#define PCCRIR_REVID_OFFS 0 /* Revision ID */ 418#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) 419 420/* Power Management Clock Gating Control Register */ 421#define MV_PEX_IF_REGS_OFFSET(if) \ 422 (if < 8 ? (0x40000 + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) \ 423 : (0x42000 + ((if) % 8) * 0x40000)) 424#define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit)) 425#define POWER_MNG_CTRL_REG 0x18220 426#define PEX_DEVICE_AND_VENDOR_ID 0x000 427#define PEX_CFG_DIRECT_ACCESS(if, reg) (MV_PEX_IF_REGS_BASE(if) + (reg)) 428#define PMC_PEXSTOPCLOCK_OFFS(port) ((port) < 8 ? (5 + (port)) : (18 + (port))) 429#define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) 430#define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) 431#define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port)) 432 433/* TWSI */ 434#define TWSI_DATA_ADDR_MASK 0x7 435#define TWSI_DATA_ADDR_OFFS 1 436 437/* General */ 438#define MAX_CS 4 439 440/* Frequencies */ 441#define FAB_OPT 21 442#define CLK_CPU 12 443#define CLK_VCO (2 * CLK_CPU) 444#define CLK_DDR 12 445 446/* Cpu Frequencies: */ 447#define CLK_CPU_1000 0 448#define CLK_CPU_1066 1 449#define CLK_CPU_1200 2 450#define CLK_CPU_1333 3 451#define CLK_CPU_1500 4 452#define CLK_CPU_1666 5 453#define CLK_CPU_1800 6 454#define CLK_CPU_2000 7 455#define CLK_CPU_600 8 456#define CLK_CPU_667 9 457#define CLK_CPU_800 0xa 458 459/* Extra Cpu Frequencies: */ 460#define CLK_CPU_1600 11 461#define CLK_CPU_2133 12 462#define CLK_CPU_2200 13 463#define CLK_CPU_2400 14 464 465/* DDR3 Frequencies: */ 466#define DDR_100 0 467#define DDR_300 1 468#define DDR_333 1 469#define DDR_360 2 470#define DDR_400 3 471#define DDR_444 4 472#define DDR_500 5 473#define DDR_533 6 474#define DDR_600 7 475#define DDR_640 8 476#define DDR_666 8 477#define DDR_720 9 478#define DDR_750 9 479#define DDR_800 10 480#define DDR_833 11 481#define DDR_HCLK 20 482#define DDR_S 12 483#define DDR_S_1TO1 13 484#define MARGIN_FREQ DDR_400 485#define DFS_MARGIN DDR_100 486 487#define ODT_OPT 16 488#define ODT20 0x200 489#define ODT30 0x204 490#define ODT40 0x44 491#define ODT120 0x40 492#define ODT120D 0x400 493 494#define MRS_DELAY 100 495 496#define SDRAM_WL_SW_OFFS 0x100 497#define SDRAM_RL_OFFS 0x0 498#define SDRAM_PBS_I_OFFS 0x140 499#define SDRAM_PBS_II_OFFS 0x180 500#define SDRAM_PBS_NEXT_OFFS (SDRAM_PBS_II_OFFS - SDRAM_PBS_I_OFFS) 501#define SDRAM_PBS_TX_OFFS 0x180 502#define SDRAM_PBS_TX_DM_OFFS 576 503#define SDRAM_DQS_RX_OFFS 1024 504#define SDRAM_DQS_TX_OFFS 2048 505#define SDRAM_DQS_RX_SPECIAL_OFFS 5120 506 507#define LEN_STD_PATTERN 16 508#define LEN_KILLER_PATTERN 128 509#define LEN_SPECIAL_PATTERN 128 510#define LEN_PBS_PATTERN 16 511 512#endif /* __DDR3_AXP_H */ 513