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6#include <cpu_func.h>
7#include <asm/io.h>
8#include <common.h>
9#include <console.h>
10#include <linux/bug.h>
11#include <linux/mii.h>
12#include <miiphy.h>
13#include <net.h>
14#include <reset.h>
15#include <wait_bit.h>
16
17#define STATION_ADDR_LOW 0x0000
18#define STATION_ADDR_HIGH 0x0004
19#define MAC_DUPLEX_HALF_CTRL 0x0008
20#define PORT_MODE 0x0040
21#define PORT_EN 0x0044
22#define BIT_TX_EN BIT(2)
23#define BIT_RX_EN BIT(1)
24#define MODE_CHANGE_EN 0x01b4
25#define BIT_MODE_CHANGE_EN BIT(0)
26#define MDIO_SINGLE_CMD 0x03c0
27#define BIT_MDIO_BUSY BIT(20)
28#define MDIO_READ (BIT(17) | BIT_MDIO_BUSY)
29#define MDIO_WRITE (BIT(16) | BIT_MDIO_BUSY)
30#define MDIO_SINGLE_DATA 0x03c4
31#define MDIO_RDATA_STATUS 0x03d0
32#define BIT_MDIO_RDATA_INVALID BIT(0)
33#define RX_FQ_START_ADDR 0x0500
34#define RX_FQ_DEPTH 0x0504
35#define RX_FQ_WR_ADDR 0x0508
36#define RX_FQ_RD_ADDR 0x050c
37#define RX_FQ_REG_EN 0x0518
38#define RX_BQ_START_ADDR 0x0520
39#define RX_BQ_DEPTH 0x0524
40#define RX_BQ_WR_ADDR 0x0528
41#define RX_BQ_RD_ADDR 0x052c
42#define RX_BQ_REG_EN 0x0538
43#define TX_BQ_START_ADDR 0x0580
44#define TX_BQ_DEPTH 0x0584
45#define TX_BQ_WR_ADDR 0x0588
46#define TX_BQ_RD_ADDR 0x058c
47#define TX_BQ_REG_EN 0x0598
48#define TX_RQ_START_ADDR 0x05a0
49#define TX_RQ_DEPTH 0x05a4
50#define TX_RQ_WR_ADDR 0x05a8
51#define TX_RQ_RD_ADDR 0x05ac
52#define TX_RQ_REG_EN 0x05b8
53#define BIT_START_ADDR_EN BIT(2)
54#define BIT_DEPTH_EN BIT(1)
55#define DESC_WR_RD_ENA 0x05cc
56#define BIT_RX_OUTCFF_WR BIT(3)
57#define BIT_RX_CFF_RD BIT(2)
58#define BIT_TX_OUTCFF_WR BIT(1)
59#define BIT_TX_CFF_RD BIT(0)
60#define BITS_DESC_ENA (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
61 BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)
62
63
64#define RGMII_SPEED_1000 0x2c
65#define RGMII_SPEED_100 0x2f
66#define RGMII_SPEED_10 0x2d
67#define MII_SPEED_100 0x0f
68#define MII_SPEED_10 0x0d
69#define GMAC_SPEED_1000 0x05
70#define GMAC_SPEED_100 0x01
71#define GMAC_SPEED_10 0x00
72#define GMAC_FULL_DUPLEX BIT(4)
73
74#define RX_DESC_NUM 64
75#define TX_DESC_NUM 2
76#define DESC_SIZE 32
77#define DESC_WORD_SHIFT 3
78#define DESC_BYTE_SHIFT 5
79#define DESC_CNT(n) ((n) >> DESC_BYTE_SHIFT)
80#define DESC_BYTE(n) ((n) << DESC_BYTE_SHIFT)
81#define DESC_VLD_FREE 0
82#define DESC_VLD_BUSY 1
83
84#define MAC_MAX_FRAME_SIZE 1600
85
86enum higmac_queue {
87 RX_FQ,
88 RX_BQ,
89 TX_BQ,
90 TX_RQ,
91};
92
93struct higmac_desc {
94 unsigned int buf_addr;
95 unsigned int buf_len:11;
96 unsigned int reserve0:5;
97 unsigned int data_len:11;
98 unsigned int reserve1:2;
99 unsigned int fl:2;
100 unsigned int descvid:1;
101 unsigned int reserve2[6];
102};
103
104struct higmac_priv {
105 void __iomem *base;
106 void __iomem *macif_ctrl;
107 struct reset_ctl rst_phy;
108 struct higmac_desc *rxfq;
109 struct higmac_desc *rxbq;
110 struct higmac_desc *txbq;
111 struct higmac_desc *txrq;
112 int rxdesc_in_use;
113 struct mii_dev *bus;
114 struct phy_device *phydev;
115 int phyintf;
116 int phyaddr;
117};
118
119#define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
120#define invalidate_desc(d) \
121 invalidate_dcache_range((unsigned long)(d), \
122 (unsigned long)(d) + sizeof(*(d)))
123
124static int higmac_write_hwaddr(struct udevice *dev)
125{
126 struct eth_pdata *pdata = dev_get_platdata(dev);
127 struct higmac_priv *priv = dev_get_priv(dev);
128 unsigned char *mac = pdata->enetaddr;
129 u32 val;
130
131 val = mac[1] | (mac[0] << 8);
132 writel(val, priv->base + STATION_ADDR_HIGH);
133
134 val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
135 writel(val, priv->base + STATION_ADDR_LOW);
136
137 return 0;
138}
139
140static int higmac_free_pkt(struct udevice *dev, uchar *packet, int length)
141{
142 struct higmac_priv *priv = dev_get_priv(dev);
143
144
145 writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);
146
147 return 0;
148}
149
150static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
151{
152 struct higmac_priv *priv = dev_get_priv(dev);
153 struct higmac_desc *fqd = priv->rxfq;
154 struct higmac_desc *bqd = priv->rxbq;
155 int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
156 int timeout = 100000;
157 int len = 0;
158 int space;
159 int i;
160
161 fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
162 fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
163
164 if (fqw_pos >= fqr_pos)
165 space = RX_DESC_NUM - (fqw_pos - fqr_pos);
166 else
167 space = fqr_pos - fqw_pos;
168
169
170 for (i = 0; i < space - 1; i++) {
171 fqd = priv->rxfq + fqw_pos;
172 invalidate_dcache_range(fqd->buf_addr,
173 fqd->buf_addr + MAC_MAX_FRAME_SIZE);
174
175 if (++fqw_pos >= RX_DESC_NUM)
176 fqw_pos = 0;
177
178 writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
179 }
180
181 bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
182 bqd += bqr_pos;
183
184 invalidate_desc(bqd);
185
186 do {
187 bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
188 udelay(1);
189 } while (--timeout && bqw_pos == bqr_pos);
190
191 if (!timeout)
192 return -ETIMEDOUT;
193
194 if (++bqr_pos >= RX_DESC_NUM)
195 bqr_pos = 0;
196
197 len = bqd->data_len;
198
199
200 invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
201 *packetp = (void *)(unsigned long)bqd->buf_addr;
202
203
204 priv->rxdesc_in_use = bqr_pos;
205
206 return len;
207}
208
209static int higmac_send(struct udevice *dev, void *packet, int length)
210{
211 struct higmac_priv *priv = dev_get_priv(dev);
212 struct higmac_desc *bqd = priv->txbq;
213 int bqw_pos, rqw_pos, rqr_pos;
214 int timeout = 1000;
215
216 flush_cache((unsigned long)packet, length);
217
218 bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
219 bqd += bqw_pos;
220 bqd->buf_addr = (unsigned long)packet;
221 bqd->descvid = DESC_VLD_BUSY;
222 bqd->data_len = length;
223 flush_desc(bqd);
224
225 if (++bqw_pos >= TX_DESC_NUM)
226 bqw_pos = 0;
227
228 writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);
229
230 rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
231 if (++rqr_pos >= TX_DESC_NUM)
232 rqr_pos = 0;
233
234 do {
235 rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
236 udelay(1);
237 } while (--timeout && rqr_pos != rqw_pos);
238
239 if (!timeout)
240 return -ETIMEDOUT;
241
242 writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);
243
244 return 0;
245}
246
247static int higmac_adjust_link(struct higmac_priv *priv)
248{
249 struct phy_device *phydev = priv->phydev;
250 int interface = priv->phyintf;
251 u32 val;
252
253 switch (interface) {
254 case PHY_INTERFACE_MODE_RGMII:
255 if (phydev->speed == SPEED_1000)
256 val = RGMII_SPEED_1000;
257 else if (phydev->speed == SPEED_100)
258 val = RGMII_SPEED_100;
259 else
260 val = RGMII_SPEED_10;
261 break;
262 case PHY_INTERFACE_MODE_MII:
263 if (phydev->speed == SPEED_100)
264 val = MII_SPEED_100;
265 else
266 val = MII_SPEED_10;
267 break;
268 default:
269 debug("unsupported mode: %d\n", interface);
270 return -EINVAL;
271 }
272
273 if (phydev->duplex)
274 val |= GMAC_FULL_DUPLEX;
275
276 writel(val, priv->macif_ctrl);
277
278 if (phydev->speed == SPEED_1000)
279 val = GMAC_SPEED_1000;
280 else if (phydev->speed == SPEED_100)
281 val = GMAC_SPEED_100;
282 else
283 val = GMAC_SPEED_10;
284
285 writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
286 writel(val, priv->base + PORT_MODE);
287 writel(0, priv->base + MODE_CHANGE_EN);
288 writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
289
290 return 0;
291}
292
293static int higmac_start(struct udevice *dev)
294{
295 struct higmac_priv *priv = dev_get_priv(dev);
296 struct phy_device *phydev = priv->phydev;
297 int ret;
298
299 ret = phy_startup(phydev);
300 if (ret)
301 return ret;
302
303 if (!phydev->link) {
304 debug("%s: link down\n", phydev->dev->name);
305 return -ENODEV;
306 }
307
308 ret = higmac_adjust_link(priv);
309 if (ret)
310 return ret;
311
312
313 writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
314 writel(BIT_TX_EN | BIT_RX_EN, priv->base + PORT_EN);
315
316 return 0;
317}
318
319static void higmac_stop(struct udevice *dev)
320{
321 struct higmac_priv *priv = dev_get_priv(dev);
322
323
324 writel(0, priv->base + PORT_EN);
325 writel(0, priv->base + DESC_WR_RD_ENA);
326}
327
328static const struct eth_ops higmac_ops = {
329 .start = higmac_start,
330 .send = higmac_send,
331 .recv = higmac_recv,
332 .free_pkt = higmac_free_pkt,
333 .stop = higmac_stop,
334 .write_hwaddr = higmac_write_hwaddr,
335};
336
337static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
338{
339 struct higmac_priv *priv = bus->priv;
340 int ret;
341
342 ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
343 false, 1000, false);
344 if (ret)
345 return ret;
346
347 writel(MDIO_READ | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
348
349 ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
350 false, 1000, false);
351 if (ret)
352 return ret;
353
354 if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
355 return -EINVAL;
356
357 return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
358}
359
360static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
361 int reg, u16 value)
362{
363 struct higmac_priv *priv = bus->priv;
364 int ret;
365
366 ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
367 false, 1000, false);
368 if (ret)
369 return ret;
370
371 writel(value, priv->base + MDIO_SINGLE_DATA);
372 writel(MDIO_WRITE | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
373
374 return 0;
375}
376
377static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
378{
379 int i;
380
381 for (i = 0; i < num; i++) {
382 struct higmac_desc *desc = &descs[i];
383
384 desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
385 MAC_MAX_FRAME_SIZE);
386 if (!desc->buf_addr)
387 goto free_bufs;
388
389 desc->descvid = DESC_VLD_FREE;
390 desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
391 flush_desc(desc);
392 }
393
394 return 0;
395
396free_bufs:
397 while (--i > 0)
398 free((void *)(unsigned long)descs[i].buf_addr);
399 return -ENOMEM;
400}
401
402static int higmac_init_hw_queue(struct higmac_priv *priv,
403 enum higmac_queue queue)
404{
405 struct higmac_desc *desc, **pdesc;
406 u32 regaddr, regen, regdep;
407 int depth;
408 int len;
409
410 switch (queue) {
411 case RX_FQ:
412 regaddr = RX_FQ_START_ADDR;
413 regen = RX_FQ_REG_EN;
414 regdep = RX_FQ_DEPTH;
415 depth = RX_DESC_NUM;
416 pdesc = &priv->rxfq;
417 break;
418 case RX_BQ:
419 regaddr = RX_BQ_START_ADDR;
420 regen = RX_BQ_REG_EN;
421 regdep = RX_BQ_DEPTH;
422 depth = RX_DESC_NUM;
423 pdesc = &priv->rxbq;
424 break;
425 case TX_BQ:
426 regaddr = TX_BQ_START_ADDR;
427 regen = TX_BQ_REG_EN;
428 regdep = TX_BQ_DEPTH;
429 depth = TX_DESC_NUM;
430 pdesc = &priv->txbq;
431 break;
432 case TX_RQ:
433 regaddr = TX_RQ_START_ADDR;
434 regen = TX_RQ_REG_EN;
435 regdep = TX_RQ_DEPTH;
436 depth = TX_DESC_NUM;
437 pdesc = &priv->txrq;
438 break;
439 }
440
441
442 writel(BIT_DEPTH_EN, priv->base + regen);
443 writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
444 writel(0, priv->base + regen);
445
446 len = depth * sizeof(*desc);
447 desc = memalign(ARCH_DMA_MINALIGN, len);
448 if (!desc)
449 return -ENOMEM;
450 memset(desc, 0, len);
451 flush_cache((unsigned long)desc, len);
452 *pdesc = desc;
453
454
455 if (queue == RX_FQ)
456 higmac_init_rx_descs(desc, depth);
457
458
459 writel(BIT_START_ADDR_EN, priv->base + regen);
460 writel((unsigned long)desc, priv->base + regaddr);
461 writel(0, priv->base + regen);
462
463 return 0;
464}
465
466static int higmac_hw_init(struct higmac_priv *priv)
467{
468 int ret;
469
470
471 ret = higmac_init_hw_queue(priv, RX_FQ);
472 if (ret)
473 return ret;
474
475 ret = higmac_init_hw_queue(priv, RX_BQ);
476 if (ret)
477 goto free_rx_fq;
478
479 ret = higmac_init_hw_queue(priv, TX_BQ);
480 if (ret)
481 goto free_rx_bq;
482
483 ret = higmac_init_hw_queue(priv, TX_RQ);
484 if (ret)
485 goto free_tx_bq;
486
487
488 reset_deassert(&priv->rst_phy);
489 mdelay(10);
490 reset_assert(&priv->rst_phy);
491 mdelay(30);
492 reset_deassert(&priv->rst_phy);
493 mdelay(30);
494
495 return 0;
496
497free_tx_bq:
498 free(priv->txbq);
499free_rx_bq:
500 free(priv->rxbq);
501free_rx_fq:
502 free(priv->rxfq);
503 return ret;
504}
505
506static int higmac_probe(struct udevice *dev)
507{
508 struct higmac_priv *priv = dev_get_priv(dev);
509 struct phy_device *phydev;
510 struct mii_dev *bus;
511 int ret;
512
513 ret = higmac_hw_init(priv);
514 if (ret)
515 return ret;
516
517 bus = mdio_alloc();
518 if (!bus)
519 return -ENOMEM;
520
521 bus->read = higmac_mdio_read;
522 bus->write = higmac_mdio_write;
523 bus->priv = priv;
524 priv->bus = bus;
525
526 ret = mdio_register_seq(bus, dev->seq);
527 if (ret)
528 return ret;
529
530 phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
531 if (!phydev)
532 return -ENODEV;
533
534 phydev->supported &= PHY_GBIT_FEATURES;
535 phydev->advertising = phydev->supported;
536 priv->phydev = phydev;
537
538 return phy_config(phydev);
539}
540
541static int higmac_remove(struct udevice *dev)
542{
543 struct higmac_priv *priv = dev_get_priv(dev);
544 int i;
545
546 mdio_unregister(priv->bus);
547 mdio_free(priv->bus);
548
549
550 for (i = 0; i < RX_DESC_NUM; i++)
551 free((void *)(unsigned long)priv->rxfq[i].buf_addr);
552
553 return 0;
554}
555
556static int higmac_ofdata_to_platdata(struct udevice *dev)
557{
558 struct higmac_priv *priv = dev_get_priv(dev);
559 int phyintf = PHY_INTERFACE_MODE_NONE;
560 const char *phy_mode;
561 ofnode phy_node;
562
563 priv->base = dev_remap_addr_index(dev, 0);
564 priv->macif_ctrl = dev_remap_addr_index(dev, 1);
565
566 phy_mode = dev_read_string(dev, "phy-mode");
567 if (phy_mode)
568 phyintf = phy_get_interface_by_name(phy_mode);
569 if (phyintf == PHY_INTERFACE_MODE_NONE)
570 return -ENODEV;
571 priv->phyintf = phyintf;
572
573 phy_node = dev_read_subnode(dev, "phy");
574 if (!ofnode_valid(phy_node)) {
575 debug("failed to find phy node\n");
576 return -ENODEV;
577 }
578 priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);
579
580 return reset_get_by_name(dev, "phy", &priv->rst_phy);
581}
582
583static const struct udevice_id higmac_ids[] = {
584 { .compatible = "hisilicon,hi3798cv200-gmac" },
585 { }
586};
587
588U_BOOT_DRIVER(eth_higmac) = {
589 .name = "eth_higmac",
590 .id = UCLASS_ETH,
591 .of_match = higmac_ids,
592 .ofdata_to_platdata = higmac_ofdata_to_platdata,
593 .probe = higmac_probe,
594 .remove = higmac_remove,
595 .ops = &higmac_ops,
596 .priv_auto_alloc_size = sizeof(struct higmac_priv),
597 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
598};
599
