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9#include <common.h>
10#include <cpu_func.h>
11#include <dm.h>
12#include <malloc.h>
13#include <miiphy.h>
14#include <regmap.h>
15#include <reset.h>
16#include <syscon.h>
17#include <wait_bit.h>
18#include <asm/gpio.h>
19#include <asm/io.h>
20#include <linux/err.h>
21#include <linux/ioport.h>
22#include <linux/mdio.h>
23#include <linux/mii.h>
24
25#include "mtk_eth.h"
26
27#define NUM_TX_DESC 24
28#define NUM_RX_DESC 24
29#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
30#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN)
31#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
32
33#define MT7530_NUM_PHYS 5
34#define MT7530_DFL_SMI_ADDR 31
35
36#define MT7530_PHY_ADDR(base, addr) \
37 (((base) + (addr)) & 0x1f)
38
39#define GDMA_FWD_TO_CPU \
40 (0x20000000 | \
41 GDM_ICS_EN | \
42 GDM_TCS_EN | \
43 GDM_UCS_EN | \
44 STRP_CRC | \
45 (DP_PDMA << MYMAC_DP_S) | \
46 (DP_PDMA << BC_DP_S) | \
47 (DP_PDMA << MC_DP_S) | \
48 (DP_PDMA << UN_DP_S))
49
50#define GDMA_FWD_DISCARD \
51 (0x20000000 | \
52 GDM_ICS_EN | \
53 GDM_TCS_EN | \
54 GDM_UCS_EN | \
55 STRP_CRC | \
56 (DP_DISCARD << MYMAC_DP_S) | \
57 (DP_DISCARD << BC_DP_S) | \
58 (DP_DISCARD << MC_DP_S) | \
59 (DP_DISCARD << UN_DP_S))
60
61struct pdma_rxd_info1 {
62 u32 PDP0;
63};
64
65struct pdma_rxd_info2 {
66 u32 PLEN1 : 14;
67 u32 LS1 : 1;
68 u32 UN_USED : 1;
69 u32 PLEN0 : 14;
70 u32 LS0 : 1;
71 u32 DDONE : 1;
72};
73
74struct pdma_rxd_info3 {
75 u32 PDP1;
76};
77
78struct pdma_rxd_info4 {
79 u32 FOE_ENTRY : 14;
80 u32 CRSN : 5;
81 u32 SP : 3;
82 u32 L4F : 1;
83 u32 L4VLD : 1;
84 u32 TACK : 1;
85 u32 IP4F : 1;
86 u32 IP4 : 1;
87 u32 IP6 : 1;
88 u32 UN_USED : 4;
89};
90
91struct pdma_rxdesc {
92 struct pdma_rxd_info1 rxd_info1;
93 struct pdma_rxd_info2 rxd_info2;
94 struct pdma_rxd_info3 rxd_info3;
95 struct pdma_rxd_info4 rxd_info4;
96};
97
98struct pdma_txd_info1 {
99 u32 SDP0;
100};
101
102struct pdma_txd_info2 {
103 u32 SDL1 : 14;
104 u32 LS1 : 1;
105 u32 BURST : 1;
106 u32 SDL0 : 14;
107 u32 LS0 : 1;
108 u32 DDONE : 1;
109};
110
111struct pdma_txd_info3 {
112 u32 SDP1;
113};
114
115struct pdma_txd_info4 {
116 u32 VLAN_TAG : 16;
117 u32 INS : 1;
118 u32 RESV : 2;
119 u32 UDF : 6;
120 u32 FPORT : 3;
121 u32 TSO : 1;
122 u32 TUI_CO : 3;
123};
124
125struct pdma_txdesc {
126 struct pdma_txd_info1 txd_info1;
127 struct pdma_txd_info2 txd_info2;
128 struct pdma_txd_info3 txd_info3;
129 struct pdma_txd_info4 txd_info4;
130};
131
132enum mtk_switch {
133 SW_NONE,
134 SW_MT7530
135};
136
137enum mtk_soc {
138 SOC_MT7623,
139 SOC_MT7629
140};
141
142struct mtk_eth_priv {
143 char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
144
145 struct pdma_txdesc *tx_ring_noc;
146 struct pdma_rxdesc *rx_ring_noc;
147
148 int rx_dma_owner_idx0;
149 int tx_cpu_owner_idx0;
150
151 void __iomem *fe_base;
152 void __iomem *gmac_base;
153 void __iomem *ethsys_base;
154
155 struct mii_dev *mdio_bus;
156 int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
157 int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
158 int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
159 int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
160 u16 val);
161
162 enum mtk_soc soc;
163 int gmac_id;
164 int force_mode;
165 int speed;
166 int duplex;
167
168 struct phy_device *phydev;
169 int phy_interface;
170 int phy_addr;
171
172 enum mtk_switch sw;
173 int (*switch_init)(struct mtk_eth_priv *priv);
174 u32 mt7530_smi_addr;
175 u32 mt7530_phy_base;
176
177 struct gpio_desc rst_gpio;
178 int mcm;
179
180 struct reset_ctl rst_fe;
181 struct reset_ctl rst_mcm;
182};
183
184static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
185{
186 writel(val, priv->fe_base + PDMA_BASE + reg);
187}
188
189static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
190 u32 set)
191{
192 clrsetbits_le32(priv->fe_base + PDMA_BASE + reg, clr, set);
193}
194
195static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
196 u32 val)
197{
198 u32 gdma_base;
199
200 if (no == 1)
201 gdma_base = GDMA2_BASE;
202 else
203 gdma_base = GDMA1_BASE;
204
205 writel(val, priv->fe_base + gdma_base + reg);
206}
207
208static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
209{
210 return readl(priv->gmac_base + reg);
211}
212
213static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
214{
215 writel(val, priv->gmac_base + reg);
216}
217
218static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
219{
220 clrsetbits_le32(priv->gmac_base + reg, clr, set);
221}
222
223static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
224 u32 set)
225{
226 clrsetbits_le32(priv->ethsys_base + reg, clr, set);
227}
228
229
230static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
231 u32 cmd, u32 st)
232{
233 int ret;
234 u32 val;
235
236 val = (st << MDIO_ST_S) |
237 ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
238 (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
239 (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
240
241 if (cmd == MDIO_CMD_WRITE)
242 val |= data & MDIO_RW_DATA_M;
243
244 mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
245
246 ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG,
247 PHY_ACS_ST, 0, 5000, 0);
248 if (ret) {
249 pr_warn("MDIO access timeout\n");
250 return ret;
251 }
252
253 if (cmd == MDIO_CMD_READ) {
254 val = mtk_gmac_read(priv, GMAC_PIAC_REG);
255 return val & MDIO_RW_DATA_M;
256 }
257
258 return 0;
259}
260
261
262static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
263{
264 return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
265}
266
267
268static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data)
269{
270 return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22);
271}
272
273
274static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
275{
276 int ret;
277
278 ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
279 if (ret)
280 return ret;
281
282 return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45,
283 MDIO_ST_C45);
284}
285
286
287static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
288 u16 reg, u16 val)
289{
290 int ret;
291
292 ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
293 if (ret)
294 return ret;
295
296 return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE,
297 MDIO_ST_C45);
298}
299
300
301static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
302 u16 reg)
303{
304 int ret;
305
306 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
307 (MMD_ADDR << MMD_CMD_S) |
308 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
309 if (ret)
310 return ret;
311
312 ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
313 if (ret)
314 return ret;
315
316 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
317 (MMD_DATA << MMD_CMD_S) |
318 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
319 if (ret)
320 return ret;
321
322 return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG);
323}
324
325
326static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
327 u16 reg, u16 val)
328{
329 int ret;
330
331 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
332 (MMD_ADDR << MMD_CMD_S) |
333 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
334 if (ret)
335 return ret;
336
337 ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
338 if (ret)
339 return ret;
340
341 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
342 (MMD_DATA << MMD_CMD_S) |
343 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
344 if (ret)
345 return ret;
346
347 return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val);
348}
349
350static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
351{
352 struct mtk_eth_priv *priv = bus->priv;
353
354 if (devad < 0)
355 return priv->mii_read(priv, addr, reg);
356 else
357 return priv->mmd_read(priv, addr, devad, reg);
358}
359
360static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
361 u16 val)
362{
363 struct mtk_eth_priv *priv = bus->priv;
364
365 if (devad < 0)
366 return priv->mii_write(priv, addr, reg, val);
367 else
368 return priv->mmd_write(priv, addr, devad, reg, val);
369}
370
371static int mtk_mdio_register(struct udevice *dev)
372{
373 struct mtk_eth_priv *priv = dev_get_priv(dev);
374 struct mii_dev *mdio_bus = mdio_alloc();
375 int ret;
376
377 if (!mdio_bus)
378 return -ENOMEM;
379
380
381 switch (priv->sw) {
382 case SW_MT7530:
383 priv->mii_read = mtk_mii_read;
384 priv->mii_write = mtk_mii_write;
385 priv->mmd_read = mtk_mmd_ind_read;
386 priv->mmd_write = mtk_mmd_ind_write;
387 break;
388 default:
389 priv->mii_read = mtk_mii_read;
390 priv->mii_write = mtk_mii_write;
391 priv->mmd_read = mtk_mmd_read;
392 priv->mmd_write = mtk_mmd_write;
393 }
394
395 mdio_bus->read = mtk_mdio_read;
396 mdio_bus->write = mtk_mdio_write;
397 snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name);
398
399 mdio_bus->priv = (void *)priv;
400
401 ret = mdio_register(mdio_bus);
402
403 if (ret)
404 return ret;
405
406 priv->mdio_bus = mdio_bus;
407
408 return 0;
409}
410
411
412
413
414
415
416
417
418
419
420static int mt7530_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
421{
422 int ret, low_word, high_word;
423
424
425 ret = mtk_mii_write(priv, priv->mt7530_smi_addr, 0x1f, reg >> 6);
426 if (ret)
427 return ret;
428
429
430 low_word = mtk_mii_read(priv, priv->mt7530_smi_addr, (reg >> 2) & 0xf);
431 if (low_word < 0)
432 return low_word;
433
434
435 high_word = mtk_mii_read(priv, priv->mt7530_smi_addr, 0x10);
436 if (high_word < 0)
437 return high_word;
438
439 if (data)
440 *data = ((u32)high_word << 16) | (low_word & 0xffff);
441
442 return 0;
443}
444
445static int mt7530_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
446{
447 int ret;
448
449
450 ret = mtk_mii_write(priv, priv->mt7530_smi_addr, 0x1f, reg >> 6);
451 if (ret)
452 return ret;
453
454
455 ret = mtk_mii_write(priv, priv->mt7530_smi_addr, (reg >> 2) & 0xf,
456 data & 0xffff);
457 if (ret)
458 return ret;
459
460
461 return mtk_mii_write(priv, priv->mt7530_smi_addr, 0x10, data >> 16);
462}
463
464static void mt7530_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
465 u32 set)
466{
467 u32 val;
468
469 mt7530_reg_read(priv, reg, &val);
470 val &= ~clr;
471 val |= set;
472 mt7530_reg_write(priv, reg, val);
473}
474
475static void mt7530_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
476{
477 u8 phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, 0);
478
479 mtk_mmd_ind_write(priv, phy_addr, 0x1f, reg, val);
480}
481
482static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
483{
484 u32 ncpo1, ssc_delta;
485
486 switch (mode) {
487 case PHY_INTERFACE_MODE_RGMII:
488 ncpo1 = 0x0c80;
489 ssc_delta = 0x87;
490 break;
491 default:
492 printf("error: xMII mode %d not supported\n", mode);
493 return -EINVAL;
494 }
495
496
497 mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0);
498
499
500 mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1,
501 (2 << RG_GSWPLL_POSDIV_200M_S) |
502 (32 << RG_GSWPLL_FBKDIV_200M_S));
503
504
505 mt7530_core_reg_write(priv, CORE_GSWPLL_GRP2,
506 (1 << RG_GSWPLL_POSDIV_500M_S) |
507 (25 << RG_GSWPLL_FBKDIV_500M_S));
508
509
510 mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1,
511 (2 << RG_GSWPLL_POSDIV_200M_S) |
512 (32 << RG_GSWPLL_FBKDIV_200M_S) |
513 RG_GSWPLL_EN_PRE);
514
515 udelay(20);
516
517 mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
518
519
520 mt7530_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1);
521 mt7530_core_reg_write(priv, CORE_PLL_GROUP6, 0);
522 mt7530_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta);
523 mt7530_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta);
524 mt7530_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
525 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
526
527 mt7530_core_reg_write(priv, CORE_PLL_GROUP2,
528 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
529 (1 << RG_SYSPLL_POSDIV_S));
530
531 mt7530_core_reg_write(priv, CORE_PLL_GROUP7,
532 RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) |
533 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
534
535
536 mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG,
537 REG_GSWCK_EN | REG_TRGMIICK_EN);
538
539 return 0;
540}
541
542static int mt7530_setup(struct mtk_eth_priv *priv)
543{
544 u16 phy_addr, phy_val;
545 u32 val;
546 int i;
547
548
549 mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
550 ETHSYS_TRGMII_CLK_SEL362_5, 0);
551
552
553 if (priv->mcm) {
554 reset_assert(&priv->rst_mcm);
555 udelay(1000);
556 reset_deassert(&priv->rst_mcm);
557 mdelay(1000);
558 } else if (dm_gpio_is_valid(&priv->rst_gpio)) {
559 dm_gpio_set_value(&priv->rst_gpio, 0);
560 udelay(1000);
561 dm_gpio_set_value(&priv->rst_gpio, 1);
562 mdelay(1000);
563 }
564
565
566 mt7530_reg_read(priv, HWTRAP_REG, &val);
567 val |= CHG_TRAP;
568 val &= ~C_MDIO_BPS;
569 mt7530_reg_write(priv, MHWTRAP_REG, val);
570
571
572 val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3;
573 priv->mt7530_phy_base = (val | 0x7) + 1;
574
575
576 for (i = 0; i < MT7530_NUM_PHYS; i++) {
577 phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, i);
578 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
579 phy_val |= BMCR_PDOWN;
580 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
581 }
582
583
584 mt7530_reg_write(priv, PCMR_REG(5), FORCE_MODE);
585 mt7530_reg_write(priv, PCMR_REG(6), FORCE_MODE);
586
587
588 mt7530_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
589 udelay(100);
590
591 val = (1 << IPG_CFG_S) |
592 MAC_MODE | FORCE_MODE |
593 MAC_TX_EN | MAC_RX_EN |
594 BKOFF_EN | BACKPR_EN |
595 (SPEED_1000M << FORCE_SPD_S) |
596 FORCE_DPX | FORCE_LINK;
597
598
599 mt7530_reg_write(priv, PCMR_REG(6), val);
600
601
602 mt7530_reg_write(priv, PCMR_REG(5), FORCE_MODE);
603
604
605 mt7530_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
606
607
608 mt7530_reg_read(priv, HWTRAP_REG, &val);
609 val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS |
610 (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) |
611 (P5_INTF_MODE_RGMII << P5_INTF_MODE_S);
612 val &= ~(C_MDIO_BPS | P6_INTF_DIS);
613 mt7530_reg_write(priv, MHWTRAP_REG, val);
614
615
616 mt7530_pad_clk_setup(priv, priv->phy_interface);
617
618
619 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
620 mt7530_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
621 (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
622
623 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
624 mt7530_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
625
626
627 for (i = 0; i < MT7530_NUM_PHYS; i++) {
628 phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, i);
629 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
630 phy_val &= ~BMCR_PDOWN;
631 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
632 }
633
634
635 for (i = 0; i < 8; i++) {
636
637 if (i != 6)
638 mt7530_reg_write(priv, PCR_REG(i),
639 (0x40 << PORT_MATRIX_S));
640 else
641 mt7530_reg_write(priv, PCR_REG(i),
642 (0x3f << PORT_MATRIX_S));
643
644
645 mt7530_reg_write(priv, PVC_REG(i),
646 (0x8100 << STAG_VPID_S) |
647 (VLAN_ATTR_USER << VLAN_ATTR_S));
648 }
649
650 return 0;
651}
652
653static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
654{
655 u16 lcl_adv = 0, rmt_adv = 0;
656 u8 flowctrl;
657 u32 mcr;
658
659 mcr = (1 << IPG_CFG_S) |
660 (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
661 MAC_MODE | FORCE_MODE |
662 MAC_TX_EN | MAC_RX_EN |
663 BKOFF_EN | BACKPR_EN;
664
665 switch (priv->phydev->speed) {
666 case SPEED_10:
667 mcr |= (SPEED_10M << FORCE_SPD_S);
668 break;
669 case SPEED_100:
670 mcr |= (SPEED_100M << FORCE_SPD_S);
671 break;
672 case SPEED_1000:
673 mcr |= (SPEED_1000M << FORCE_SPD_S);
674 break;
675 };
676
677 if (priv->phydev->link)
678 mcr |= FORCE_LINK;
679
680 if (priv->phydev->duplex) {
681 mcr |= FORCE_DPX;
682
683 if (priv->phydev->pause)
684 rmt_adv = LPA_PAUSE_CAP;
685 if (priv->phydev->asym_pause)
686 rmt_adv |= LPA_PAUSE_ASYM;
687
688 if (priv->phydev->advertising & ADVERTISED_Pause)
689 lcl_adv |= ADVERTISE_PAUSE_CAP;
690 if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
691 lcl_adv |= ADVERTISE_PAUSE_ASYM;
692
693 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
694
695 if (flowctrl & FLOW_CTRL_TX)
696 mcr |= FORCE_TX_FC;
697 if (flowctrl & FLOW_CTRL_RX)
698 mcr |= FORCE_RX_FC;
699
700 debug("rx pause %s, tx pause %s\n",
701 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
702 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
703 }
704
705 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
706}
707
708static int mtk_phy_start(struct mtk_eth_priv *priv)
709{
710 struct phy_device *phydev = priv->phydev;
711 int ret;
712
713 ret = phy_startup(phydev);
714
715 if (ret) {
716 debug("Could not initialize PHY %s\n", phydev->dev->name);
717 return ret;
718 }
719
720 if (!phydev->link) {
721 debug("%s: link down.\n", phydev->dev->name);
722 return 0;
723 }
724
725 mtk_phy_link_adjust(priv);
726
727 debug("Speed: %d, %s duplex%s\n", phydev->speed,
728 (phydev->duplex) ? "full" : "half",
729 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
730
731 return 0;
732}
733
734static int mtk_phy_probe(struct udevice *dev)
735{
736 struct mtk_eth_priv *priv = dev_get_priv(dev);
737 struct phy_device *phydev;
738
739 phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev,
740 priv->phy_interface);
741 if (!phydev)
742 return -ENODEV;
743
744 phydev->supported &= PHY_GBIT_FEATURES;
745 phydev->advertising = phydev->supported;
746
747 priv->phydev = phydev;
748 phy_config(phydev);
749
750 return 0;
751}
752
753static void mtk_mac_init(struct mtk_eth_priv *priv)
754{
755 int i, ge_mode = 0;
756 u32 mcr;
757
758 switch (priv->phy_interface) {
759 case PHY_INTERFACE_MODE_RGMII_RXID:
760 case PHY_INTERFACE_MODE_RGMII:
761 case PHY_INTERFACE_MODE_SGMII:
762 ge_mode = GE_MODE_RGMII;
763 break;
764 case PHY_INTERFACE_MODE_MII:
765 case PHY_INTERFACE_MODE_GMII:
766 ge_mode = GE_MODE_MII;
767 break;
768 case PHY_INTERFACE_MODE_RMII:
769 ge_mode = GE_MODE_RMII;
770 break;
771 default:
772 break;
773 }
774
775
776 mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
777 SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
778 ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id));
779
780 if (priv->force_mode) {
781 mcr = (1 << IPG_CFG_S) |
782 (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
783 MAC_MODE | FORCE_MODE |
784 MAC_TX_EN | MAC_RX_EN |
785 BKOFF_EN | BACKPR_EN |
786 FORCE_LINK;
787
788 switch (priv->speed) {
789 case SPEED_10:
790 mcr |= SPEED_10M << FORCE_SPD_S;
791 break;
792 case SPEED_100:
793 mcr |= SPEED_100M << FORCE_SPD_S;
794 break;
795 case SPEED_1000:
796 mcr |= SPEED_1000M << FORCE_SPD_S;
797 break;
798 }
799
800 if (priv->duplex)
801 mcr |= FORCE_DPX;
802
803 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
804 }
805
806 if (priv->soc == SOC_MT7623) {
807
808 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
809 mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i),
810 (8 << TD_DM_DRVP_S) |
811 (8 << TD_DM_DRVN_S));
812
813 mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0,
814 RX_RST | RXC_DQSISEL);
815 mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0);
816 }
817}
818
819static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
820{
821 char *pkt_base = priv->pkt_pool;
822 int i;
823
824 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0);
825 udelay(500);
826
827 memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc));
828 memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc));
829 memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE);
830
831 flush_dcache_range((u32)pkt_base, (u32)(pkt_base + TOTAL_PKT_BUF_SIZE));
832
833 priv->rx_dma_owner_idx0 = 0;
834 priv->tx_cpu_owner_idx0 = 0;
835
836 for (i = 0; i < NUM_TX_DESC; i++) {
837 priv->tx_ring_noc[i].txd_info2.LS0 = 1;
838 priv->tx_ring_noc[i].txd_info2.DDONE = 1;
839 priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1;
840
841 priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base);
842 pkt_base += PKTSIZE_ALIGN;
843 }
844
845 for (i = 0; i < NUM_RX_DESC; i++) {
846 priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
847 priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base);
848 pkt_base += PKTSIZE_ALIGN;
849 }
850
851 mtk_pdma_write(priv, TX_BASE_PTR_REG(0),
852 virt_to_phys(priv->tx_ring_noc));
853 mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC);
854 mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
855
856 mtk_pdma_write(priv, RX_BASE_PTR_REG(0),
857 virt_to_phys(priv->rx_ring_noc));
858 mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC);
859 mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1);
860
861 mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0);
862}
863
864static int mtk_eth_start(struct udevice *dev)
865{
866 struct mtk_eth_priv *priv = dev_get_priv(dev);
867 int ret;
868
869
870 reset_assert(&priv->rst_fe);
871 udelay(1000);
872 reset_deassert(&priv->rst_fe);
873 mdelay(10);
874
875
876 mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
877
878 if (priv->gmac_id == 0)
879 mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
880 else
881 mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
882
883 udelay(500);
884
885 mtk_eth_fifo_init(priv);
886
887
888 if (priv->sw == SW_NONE) {
889 ret = mtk_phy_start(priv);
890 if (ret)
891 return ret;
892 }
893
894 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0,
895 TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
896 udelay(500);
897
898 return 0;
899}
900
901static void mtk_eth_stop(struct udevice *dev)
902{
903 struct mtk_eth_priv *priv = dev_get_priv(dev);
904
905 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
906 TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
907 udelay(500);
908
909 wait_for_bit_le32(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG_REG,
910 RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0);
911}
912
913static int mtk_eth_write_hwaddr(struct udevice *dev)
914{
915 struct eth_pdata *pdata = dev_get_platdata(dev);
916 struct mtk_eth_priv *priv = dev_get_priv(dev);
917 unsigned char *mac = pdata->enetaddr;
918 u32 macaddr_lsb, macaddr_msb;
919
920 macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1];
921 macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) |
922 ((u32)mac[4] << 8) | (u32)mac[5];
923
924 mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb);
925 mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb);
926
927 return 0;
928}
929
930static int mtk_eth_send(struct udevice *dev, void *packet, int length)
931{
932 struct mtk_eth_priv *priv = dev_get_priv(dev);
933 u32 idx = priv->tx_cpu_owner_idx0;
934 void *pkt_base;
935
936 if (!priv->tx_ring_noc[idx].txd_info2.DDONE) {
937 debug("mtk-eth: TX DMA descriptor ring is full\n");
938 return -EPERM;
939 }
940
941 pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0);
942 memcpy(pkt_base, packet, length);
943 flush_dcache_range((u32)pkt_base, (u32)pkt_base +
944 roundup(length, ARCH_DMA_MINALIGN));
945
946 priv->tx_ring_noc[idx].txd_info2.SDL0 = length;
947 priv->tx_ring_noc[idx].txd_info2.DDONE = 0;
948
949 priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
950 mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
951
952 return 0;
953}
954
955static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
956{
957 struct mtk_eth_priv *priv = dev_get_priv(dev);
958 u32 idx = priv->rx_dma_owner_idx0;
959 uchar *pkt_base;
960 u32 length;
961
962 if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) {
963 debug("mtk-eth: RX DMA descriptor ring is empty\n");
964 return -EAGAIN;
965 }
966
967 length = priv->rx_ring_noc[idx].rxd_info2.PLEN0;
968 pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0);
969 invalidate_dcache_range((u32)pkt_base, (u32)pkt_base +
970 roundup(length, ARCH_DMA_MINALIGN));
971
972 if (packetp)
973 *packetp = pkt_base;
974
975 return length;
976}
977
978static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
979{
980 struct mtk_eth_priv *priv = dev_get_priv(dev);
981 u32 idx = priv->rx_dma_owner_idx0;
982
983 priv->rx_ring_noc[idx].rxd_info2.DDONE = 0;
984 priv->rx_ring_noc[idx].rxd_info2.LS0 = 0;
985 priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
986
987 mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx);
988 priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC;
989
990 return 0;
991}
992
993static int mtk_eth_probe(struct udevice *dev)
994{
995 struct eth_pdata *pdata = dev_get_platdata(dev);
996 struct mtk_eth_priv *priv = dev_get_priv(dev);
997 u32 iobase = pdata->iobase;
998 int ret;
999
1000
1001 priv->fe_base = (void *)iobase;
1002
1003
1004 priv->gmac_base = (void *)(iobase + GMAC_BASE);
1005
1006
1007 ret = mtk_mdio_register(dev);
1008 if (ret)
1009 return ret;
1010
1011
1012 priv->tx_ring_noc = (struct pdma_txdesc *)
1013 noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC,
1014 ARCH_DMA_MINALIGN);
1015 priv->rx_ring_noc = (struct pdma_rxdesc *)
1016 noncached_alloc(sizeof(struct pdma_rxdesc) * NUM_RX_DESC,
1017 ARCH_DMA_MINALIGN);
1018
1019
1020 mtk_mac_init(priv);
1021
1022
1023 if (priv->sw == SW_NONE)
1024 return mtk_phy_probe(dev);
1025
1026
1027 return priv->switch_init(priv);
1028}
1029
1030static int mtk_eth_remove(struct udevice *dev)
1031{
1032 struct mtk_eth_priv *priv = dev_get_priv(dev);
1033
1034
1035 mdio_unregister(priv->mdio_bus);
1036 mdio_free(priv->mdio_bus);
1037
1038
1039 mtk_eth_stop(dev);
1040
1041 return 0;
1042}
1043
1044static int mtk_eth_ofdata_to_platdata(struct udevice *dev)
1045{
1046 struct eth_pdata *pdata = dev_get_platdata(dev);
1047 struct mtk_eth_priv *priv = dev_get_priv(dev);
1048 struct ofnode_phandle_args args;
1049 struct regmap *regmap;
1050 const char *str;
1051 ofnode subnode;
1052 int ret;
1053
1054 priv->soc = dev_get_driver_data(dev);
1055
1056 pdata->iobase = devfdt_get_addr(dev);
1057
1058
1059 ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0,
1060 &args);
1061 if (ret)
1062 return ret;
1063
1064 regmap = syscon_node_to_regmap(args.node);
1065 if (IS_ERR(regmap))
1066 return PTR_ERR(regmap);
1067
1068 priv->ethsys_base = regmap_get_range(regmap, 0);
1069 if (!priv->ethsys_base) {
1070 dev_err(dev, "Unable to find ethsys\n");
1071 return -ENODEV;
1072 }
1073
1074
1075 ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
1076 if (ret) {
1077 printf("error: Unable to get reset ctrl for frame engine\n");
1078 return ret;
1079 }
1080
1081 priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0);
1082
1083
1084 str = dev_read_string(dev, "phy-mode");
1085 if (str) {
1086 pdata->phy_interface = phy_get_interface_by_name(str);
1087 priv->phy_interface = pdata->phy_interface;
1088 } else {
1089 printf("error: phy-mode is not set\n");
1090 return -EINVAL;
1091 }
1092
1093
1094 subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link");
1095 if (ofnode_valid(subnode)) {
1096 priv->force_mode = 1;
1097 priv->speed = ofnode_read_u32_default(subnode, "speed", 0);
1098 priv->duplex = ofnode_read_bool(subnode, "full-duplex");
1099
1100 if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
1101 priv->speed != SPEED_1000) {
1102 printf("error: no valid speed set in fixed-link\n");
1103 return -EINVAL;
1104 }
1105 }
1106
1107
1108 priv->sw = SW_NONE;
1109 priv->switch_init = NULL;
1110 str = dev_read_string(dev, "mediatek,switch");
1111
1112 if (str) {
1113 if (!strcmp(str, "mt7530")) {
1114 priv->sw = SW_MT7530;
1115 priv->switch_init = mt7530_setup;
1116 priv->mt7530_smi_addr = MT7530_DFL_SMI_ADDR;
1117 } else {
1118 printf("error: unsupported switch\n");
1119 return -EINVAL;
1120 }
1121
1122 priv->mcm = dev_read_bool(dev, "mediatek,mcm");
1123 if (priv->mcm) {
1124 ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm);
1125 if (ret) {
1126 printf("error: no reset ctrl for mcm\n");
1127 return ret;
1128 }
1129 } else {
1130 gpio_request_by_name(dev, "reset-gpios", 0,
1131 &priv->rst_gpio, GPIOD_IS_OUT);
1132 }
1133 } else {
1134 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0,
1135 0, &args);
1136 if (ret) {
1137 printf("error: phy-handle is not specified\n");
1138 return ret;
1139 }
1140
1141 priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1);
1142 if (priv->phy_addr < 0) {
1143 printf("error: phy address is not specified\n");
1144 return ret;
1145 }
1146 }
1147
1148 return 0;
1149}
1150
1151static const struct udevice_id mtk_eth_ids[] = {
1152 { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
1153 { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
1154 {}
1155};
1156
1157static const struct eth_ops mtk_eth_ops = {
1158 .start = mtk_eth_start,
1159 .stop = mtk_eth_stop,
1160 .send = mtk_eth_send,
1161 .recv = mtk_eth_recv,
1162 .free_pkt = mtk_eth_free_pkt,
1163 .write_hwaddr = mtk_eth_write_hwaddr,
1164};
1165
1166U_BOOT_DRIVER(mtk_eth) = {
1167 .name = "mtk-eth",
1168 .id = UCLASS_ETH,
1169 .of_match = mtk_eth_ids,
1170 .ofdata_to_platdata = mtk_eth_ofdata_to_platdata,
1171 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1172 .probe = mtk_eth_probe,
1173 .remove = mtk_eth_remove,
1174 .ops = &mtk_eth_ops,
1175 .priv_auto_alloc_size = sizeof(struct mtk_eth_priv),
1176 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1177};
1178
