1
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4
5
6#include <common.h>
7#include <env.h>
8#include <malloc.h>
9#include <asm/fsl_serdes.h>
10
11DECLARE_GLOBAL_DATA_PTR;
12
13
14
15
16
17
18
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24
25
26
27#include <pci.h>
28#include <asm/io.h>
29#include <asm/fsl_pci.h>
30
31#ifndef CONFIG_SYS_PCI_MEMORY_BUS
32#define CONFIG_SYS_PCI_MEMORY_BUS 0
33#endif
34
35#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
36#define CONFIG_SYS_PCI_MEMORY_PHYS 0
37#endif
38
39#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
40#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
41#endif
42
43
44
45
46
47static void set_inbound_window(volatile pit_t *pi,
48 struct pci_region *r,
49 u64 size)
50{
51 u32 sz = (__ilog2_u64(size) - 1);
52#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
53 u32 flag = 0;
54#else
55 u32 flag = PIWAR_LOCAL;
56#endif
57
58 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
59
60 out_be32(&pi->pitar, r->phys_start >> 12);
61 out_be32(&pi->piwbar, r->bus_start >> 12);
62#ifdef CONFIG_SYS_PCI_64BIT
63 out_be32(&pi->piwbear, r->bus_start >> 44);
64#else
65 out_be32(&pi->piwbear, 0);
66#endif
67 if (r->flags & PCI_REGION_PREFETCH)
68 flag |= PIWAR_PF;
69 out_be32(&pi->piwar, flag | sz);
70}
71
72int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
73{
74 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
75
76
77 memset(hose, 0, sizeof(struct pci_controller));
78
79 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
80
81 return fsl_is_pci_agent(hose);
82}
83
84static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
85 u64 out_lo, u8 pcie_cap,
86 volatile pit_t *pi)
87{
88 struct pci_region *r = hose->regions + hose->region_count;
89 u64 sz = min((u64)gd->ram_size, (1ull << 32));
90
91 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
92 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
93 pci_size_t pci_sz;
94
95
96 if (bus_start > out_lo) {
97 printf ("no space for inbound mapping of memory\n");
98 return 0;
99 }
100
101
102 if ((bus_start + sz) > out_lo) {
103 sz = out_lo - bus_start;
104 debug ("limiting size to %llx\n", sz);
105 }
106
107 pci_sz = 1ull << __ilog2_u64(sz);
108
109
110
111
112 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
113 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
114 (u64)bus_start, (u64)phys_start, (u64)sz);
115 pci_set_region(r, bus_start, phys_start, sz,
116 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
117 PCI_REGION_PREFETCH);
118
119
120
121
122
123 if (pci_sz != sz)
124 sz = 2ull << __ilog2_u64(sz);
125
126 set_inbound_window(pi--, r++, sz);
127 sz = 0;
128 } else {
129 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
130 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
131 pci_set_region(r, bus_start, phys_start, pci_sz,
132 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
133 PCI_REGION_PREFETCH);
134 set_inbound_window(pi--, r++, pci_sz);
135
136 sz -= pci_sz;
137 bus_start += pci_sz;
138 phys_start += pci_sz;
139
140 pci_sz = 1ull << __ilog2_u64(sz);
141 if (sz) {
142 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
143 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
144 pci_set_region(r, bus_start, phys_start, pci_sz,
145 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
146 PCI_REGION_PREFETCH);
147 set_inbound_window(pi--, r++, pci_sz);
148 sz -= pci_sz;
149 bus_start += pci_sz;
150 phys_start += pci_sz;
151 }
152 }
153
154#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
155
156
157
158
159 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
160
161 if (gd->ram_size > pci_sz)
162 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
163 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
164 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
165 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
166 (u64)pci_sz);
167 pci_set_region(r,
168 CONFIG_SYS_PCI64_MEMORY_BUS,
169 CONFIG_SYS_PCI_MEMORY_PHYS,
170 pci_sz,
171 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
172 PCI_REGION_PREFETCH);
173 set_inbound_window(pi--, r++, pci_sz);
174#else
175 pci_sz = 1ull << __ilog2_u64(sz);
176 if (sz) {
177 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
178 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
179 pci_set_region(r, bus_start, phys_start, pci_sz,
180 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
181 PCI_REGION_PREFETCH);
182 sz -= pci_sz;
183 bus_start += pci_sz;
184 phys_start += pci_sz;
185 set_inbound_window(pi--, r++, pci_sz);
186 }
187#endif
188
189#ifdef CONFIG_PHYS_64BIT
190 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
191 printf("Was not able to map all of memory via "
192 "inbound windows -- %lld remaining\n", sz);
193#endif
194
195 hose->region_count = r - hose->regions;
196
197 return 1;
198}
199
200#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
201static void fsl_pcie_boot_master(pit_t *pi)
202{
203
204 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
205 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
206 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
207 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
208 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
209 struct pci_region r_inbound;
210 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
211 - 1;
212 pci_set_region(&r_inbound,
213 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
214 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
215 sz_inbound,
216 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
217
218 set_inbound_window(pi--, &r_inbound,
219 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
220
221
222 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
223 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
224 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
225 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
226 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
227 pci_set_region(&r_inbound,
228 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
229 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
230 sz_inbound,
231 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
232
233 set_inbound_window(pi--, &r_inbound,
234 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
235
236
237 debug("PCIEBOOT - MASTER: Inbound window for slave's "
238 "ucode and ENV; "
239 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
240 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
241 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
242 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
243 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
244 - 1;
245 pci_set_region(&r_inbound,
246 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
247 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
248 sz_inbound,
249 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
250
251 set_inbound_window(pi--, &r_inbound,
252 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
253}
254
255static void fsl_pcie_boot_master_release_slave(int port)
256{
257 unsigned long release_addr;
258
259
260 switch (port) {
261 case 1:
262 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
263 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
264 break;
265#ifdef CONFIG_SYS_PCIE2_MEM_VIRT
266 case 2:
267 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
268 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
269 break;
270#endif
271#ifdef CONFIG_SYS_PCIE3_MEM_VIRT
272 case 3:
273 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
274 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
275 break;
276#endif
277 default:
278 release_addr = 0;
279 break;
280 }
281 if (release_addr != 0) {
282 out_be32((void *)release_addr,
283 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
284 debug("PCIEBOOT - MASTER: "
285 "Release slave successfully! Now the slave should start up!\n");
286 } else {
287 debug("PCIEBOOT - MASTER: "
288 "Release slave failed!\n");
289 }
290}
291#endif
292
293void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
294{
295 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
296 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
297 u16 temp16;
298 u32 temp32;
299 u32 block_rev;
300 int enabled, r, inbound = 0;
301 u16 ltssm;
302 u8 temp8, pcie_cap;
303 int pcie_cap_pos;
304 int pci_dcr;
305 int pci_dsr;
306 int pci_lsr;
307
308#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
309 int pci_lcr;
310#endif
311
312 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
313 struct pci_region *reg = hose->regions + hose->region_count;
314 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
315
316
317 volatile pot_t *po = &pci->pot[1];
318 volatile pit_t *pi;
319
320 u64 out_hi = 0, out_lo = -1ULL;
321 u32 pcicsrbar, pcicsrbar_sz;
322
323 pci_setup_indirect(hose, cfg_addr, cfg_data);
324
325#ifdef PEX_CCB_DIV
326
327 pci_hose_write_config_dword(hose, dev, 0x440,
328 ((gd->bus_clk / 1000000) *
329 (16 / PEX_CCB_DIV)) / 333);
330#endif
331 block_rev = in_be32(&pci->block_rev1);
332 if (PEX_IP_BLK_REV_2_2 <= block_rev) {
333 pi = &pci->pit[2];
334 } else {
335 pi = &pci->pit[3];
336 }
337
338
339 for (r = 0; r < hose->region_count; r++) {
340 unsigned long flags = hose->regions[r].flags;
341 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
342
343 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
344 if (flags != PCI_REGION_SYS_MEMORY) {
345 u64 start = hose->regions[r].bus_start;
346 u64 end = start + hose->regions[r].size;
347
348 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
349 out_be32(&po->potar, start >> 12);
350#ifdef CONFIG_SYS_PCI_64BIT
351 out_be32(&po->potear, start >> 44);
352#else
353 out_be32(&po->potear, 0);
354#endif
355 if (hose->regions[r].flags & PCI_REGION_IO) {
356 out_be32(&po->powar, POWAR_EN | sz |
357 POWAR_IO_READ | POWAR_IO_WRITE);
358 } else {
359 out_be32(&po->powar, POWAR_EN | sz |
360 POWAR_MEM_READ | POWAR_MEM_WRITE);
361 out_lo = min(start, out_lo);
362 out_hi = max(end, out_hi);
363 }
364 po++;
365 }
366 }
367 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
368
369
370 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
371 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
372 pcicsrbar_sz = ~pcicsrbar_sz + 1;
373
374 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
375 (out_lo > 0x100000000ull))
376 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
377 else
378 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
379 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
380
381 out_lo = min(out_lo, (u64)pcicsrbar);
382
383 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
384
385 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
386 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
387 hose->region_count++;
388
389
390 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
391 pci_dcr = pcie_cap_pos + 0x08;
392 pci_dsr = pcie_cap_pos + 0x0a;
393 pci_lsr = pcie_cap_pos + 0x12;
394
395 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
396
397#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
398
399 char *s = env_get("bootmaster");
400 char pcie[6];
401 sprintf(pcie, "PCIE%d", pci_info->pci_num);
402
403 if (s && (strcmp(s, pcie) == 0)) {
404 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
405 pci_info->pci_num);
406 fsl_pcie_boot_master((pit_t *)pi);
407 } else {
408
409 inbound = fsl_pci_setup_inbound_windows(hose,
410 out_lo, pcie_cap, pi);
411 }
412#else
413
414 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
415#endif
416
417 for (r = 0; r < hose->region_count; r++)
418 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
419 (u64)hose->regions[r].phys_start,
420 (u64)hose->regions[r].bus_start,
421 (u64)hose->regions[r].size,
422 hose->regions[r].flags);
423
424 pci_register_hose(hose);
425 pciauto_config_init(hose);
426 hose->current_busno = hose->first_busno;
427
428 out_be32(&pci->pedr, 0xffffffff);
429 out_be32(&pci->peer, ~0x20140);
430
431
432
433
434 pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
435 temp32 |= 0xf000e;
436 pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
437
438#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
439 pci_lcr = pcie_cap_pos + 0x10;
440 temp32 = 0;
441 pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
442 temp32 &= ~0x03;
443 pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
444 udelay(1);
445#endif
446 if (pcie_cap == PCI_CAP_ID_EXP) {
447 if (block_rev >= PEX_IP_BLK_REV_3_0) {
448#define PEX_CSR0_LTSSM_MASK 0xFC
449#define PEX_CSR0_LTSSM_SHIFT 2
450 ltssm = (in_be32(&pci->pex_csr0)
451 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
452 enabled = (ltssm == 0x11) ? 1 : 0;
453#ifdef CONFIG_FSL_PCIE_RESET
454 int i;
455
456 setbits_be32(&pci->pdb_stat, 0x08000000);
457 (void) in_be32(&pci->pdb_stat);
458 udelay(1000);
459
460 clrbits_be32(&pci->pdb_stat, 0x08000000);
461 asm("sync;isync");
462 for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
463 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
464 <ssm);
465 udelay(1000);
466 }
467#endif
468 } else {
469
470
471 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
472 enabled = ltssm >= PCI_LTSSM_L0;
473
474#ifdef CONFIG_FSL_PCIE_RESET
475 if (ltssm == 1) {
476 int i;
477 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
478
479 setbits_be32(&pci->pdb_stat, 0x08000000);
480 (void) in_be32(&pci->pdb_stat);
481 udelay(100);
482 debug(" Asserting PCIe reset @%p = %x\n",
483 &pci->pdb_stat, in_be32(&pci->pdb_stat));
484
485 clrbits_be32(&pci->pdb_stat, 0x08000000);
486 asm("sync;isync");
487 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
488 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
489 <ssm);
490 udelay(1000);
491 debug("....PCIe link error. "
492 "LTSSM=0x%02x.\n", ltssm);
493 }
494 enabled = ltssm >= PCI_LTSSM_L0;
495
496
497
498
499 pci_hose_write_config_dword(hose, dev,
500 PCI_BASE_ADDRESS_0, pcicsrbar);
501 }
502#endif
503 }
504
505#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
506 if (enabled == 0) {
507 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
508 temp32 = in_be32(&srds_regs->srdspccr0);
509
510 if ((temp32 >> 28) == 3) {
511 int i;
512
513 out_be32(&srds_regs->srdspccr0, 2 << 28);
514 setbits_be32(&pci->pdb_stat, 0x08000000);
515 in_be32(&pci->pdb_stat);
516 udelay(100);
517 clrbits_be32(&pci->pdb_stat, 0x08000000);
518 asm("sync;isync");
519 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
520 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
521 udelay(1000);
522 }
523 enabled = ltssm >= PCI_LTSSM_L0;
524 }
525 }
526#endif
527 if (!enabled) {
528
529
530
531
532 if (fsl_is_pci_agent(hose))
533 printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
534 else
535 printf("no link, regs @ 0x%lx\n", pci_info->regs);
536 hose->last_busno = hose->first_busno;
537 return;
538 }
539
540 out_be32(&pci->pme_msg_det, 0xffffffff);
541 out_be32(&pci->pme_msg_int_en, 0xffffffff);
542
543
544 pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
545 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
546 (temp16 & 0xf), pci_info->regs);
547
548 hose->current_busno++;
549 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
550 }
551
552#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
553
554
555
556 clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
557#endif
558
559
560
561
562
563 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
564 hose->pci_prefetch, hose->pci_io);
565
566 if (inbound) {
567 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
568 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
569 temp16 | PCI_COMMAND_MEMORY);
570 }
571
572#ifndef CONFIG_PCI_NOSCAN
573 if (!fsl_is_pci_agent(hose)) {
574 debug(" Scanning PCI bus %02x\n",
575 hose->current_busno);
576 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
577 } else {
578 debug(" Not scanning PCI bus %02x. PI=%x\n",
579 hose->current_busno, temp8);
580 hose->last_busno = hose->current_busno;
581 }
582
583
584
585
586 if (pcie_cap == PCI_CAP_ID_EXP) {
587 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
588 }
589#else
590 hose->last_busno = hose->current_busno;
591#endif
592
593
594 if (pcie_cap == PCI_CAP_ID_EXP)
595 out_be32(&pci->pme_msg_det, 0xffffffff);
596 out_be32(&pci->pedr, 0xffffffff);
597
598 pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
599 if (temp16) {
600 pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
601 }
602
603 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
604 if (temp16) {
605 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
606 }
607}
608
609int fsl_is_pci_agent(struct pci_controller *hose)
610{
611 int pcie_cap_pos;
612 u8 pcie_cap;
613 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
614
615 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
616 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
617 if (pcie_cap == PCI_CAP_ID_EXP) {
618 u8 header_type;
619
620 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
621 &header_type);
622 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
623 } else {
624 u8 prog_if;
625
626 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
627
628
629
630
631 return (prog_if == FSL_PROG_IF_AGENT);
632 }
633}
634
635int fsl_pci_init_port(struct fsl_pci_info *pci_info,
636 struct pci_controller *hose, int busno)
637{
638 volatile ccsr_fsl_pci_t *pci;
639 struct pci_region *r;
640 pci_dev_t dev = PCI_BDF(busno,0,0);
641 int pcie_cap_pos;
642 u8 pcie_cap;
643
644 pci = (ccsr_fsl_pci_t *) pci_info->regs;
645
646
647
648
649 if (in_be32(&pci->pme_msg_det)) {
650 out_be32(&pci->pme_msg_det, 0xffffffff);
651 debug (" with errors. Clearing. Now 0x%08x",
652 pci->pme_msg_det);
653 }
654
655 r = hose->regions + hose->region_count;
656
657
658 pci_set_region(r++,
659 pci_info->mem_bus,
660 pci_info->mem_phys,
661 pci_info->mem_size,
662 PCI_REGION_MEM);
663
664
665 pci_set_region(r++,
666 pci_info->io_bus,
667 pci_info->io_phys,
668 pci_info->io_size,
669 PCI_REGION_IO);
670
671 hose->region_count = r - hose->regions;
672 hose->first_busno = busno;
673
674 fsl_pci_init(hose, pci_info);
675
676 if (fsl_is_pci_agent(hose)) {
677 fsl_pci_config_unlock(hose);
678 hose->last_busno = hose->first_busno;
679#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
680 } else {
681
682 char *s = env_get("bootmaster");
683 char pcie[6];
684 sprintf(pcie, "PCIE%d", pci_info->pci_num);
685
686 if (s && (strcmp(s, pcie) == 0))
687 fsl_pcie_boot_master_release_slave(pci_info->pci_num);
688#endif
689 }
690
691 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
692 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
693 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
694 "e" : "", pci_info->pci_num,
695 hose->first_busno, hose->last_busno);
696 return(hose->last_busno + 1);
697}
698
699
700void fsl_pci_config_unlock(struct pci_controller *hose)
701{
702 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
703 int pcie_cap_pos;
704 u8 pcie_cap;
705 u16 pbfr;
706
707 if (!fsl_is_pci_agent(hose))
708 return;
709
710 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
711 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
712 if (pcie_cap != 0x0) {
713 ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
714 u32 block_rev = in_be32(&pci->block_rev1);
715
716 if (block_rev >= PEX_IP_BLK_REV_3_0)
717 setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
718 else
719 pci_hose_write_config_byte(hose, dev,
720 FSL_PCIE_CFG_RDY, 0x1);
721 } else {
722
723 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
724 pbfr &= ~0x20;
725 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
726 }
727}
728
729#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
730 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
731int fsl_configure_pcie(struct fsl_pci_info *info,
732 struct pci_controller *hose,
733 const char *connected, int busno)
734{
735 int is_endpoint;
736
737 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
738 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
739
740 is_endpoint = fsl_setup_hose(hose, info->regs);
741 printf("PCIe%u: %s", info->pci_num,
742 is_endpoint ? "Endpoint" : "Root Complex");
743 if (connected)
744 printf(" of %s", connected);
745 puts(", ");
746
747 return fsl_pci_init_port(info, hose, busno);
748}
749
750#if defined(CONFIG_FSL_CORENET)
751#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
752 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
753 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
754 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
755 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
756#else
757 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
758 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
759 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
760 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
761#endif
762 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
763#elif defined(CONFIG_MPC85xx)
764 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
765 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
766 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
767 #define _DEVDISR_PCIE4 0
768 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
769#elif defined(CONFIG_MPC86xx)
770 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
771 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
772 #define _DEVDISR_PCIE3 0
773 #define _DEVDISR_PCIE4 0
774 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
775 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
776#else
777#error "No defines for DEVDISR_PCIE"
778#endif
779
780
781static const char *__board_serdes_name(enum srds_prtcl device)
782{
783 switch (device) {
784#ifdef CONFIG_SYS_PCIE1_NAME
785 case PCIE1:
786 return CONFIG_SYS_PCIE1_NAME;
787#endif
788#ifdef CONFIG_SYS_PCIE2_NAME
789 case PCIE2:
790 return CONFIG_SYS_PCIE2_NAME;
791#endif
792#ifdef CONFIG_SYS_PCIE3_NAME
793 case PCIE3:
794 return CONFIG_SYS_PCIE3_NAME;
795#endif
796#ifdef CONFIG_SYS_PCIE4_NAME
797 case PCIE4:
798 return CONFIG_SYS_PCIE4_NAME;
799#endif
800 default:
801 return NULL;
802 }
803
804 return NULL;
805}
806
807__attribute__((weak, alias("__board_serdes_name"))) const char *
808board_serdes_name(enum srds_prtcl device);
809
810static u32 devdisr_mask[] = {
811 _DEVDISR_PCIE1,
812 _DEVDISR_PCIE2,
813 _DEVDISR_PCIE3,
814 _DEVDISR_PCIE4,
815};
816
817int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
818 struct fsl_pci_info *pci_info)
819{
820 struct pci_controller *hose;
821 int num = dev - PCIE1;
822
823 hose = calloc(1, sizeof(struct pci_controller));
824 if (!hose)
825 return busno;
826
827 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
828 busno = fsl_configure_pcie(pci_info, hose,
829 board_serdes_name(dev), busno);
830 } else {
831 printf("PCIe%d: disabled\n", num + 1);
832 }
833
834 return busno;
835}
836
837int fsl_pcie_init_board(int busno)
838{
839 struct fsl_pci_info pci_info;
840 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
841 u32 devdisr;
842 u32 *addr;
843
844#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
845 addr = &gur->devdisr3;
846#else
847 addr = &gur->devdisr;
848#endif
849 devdisr = in_be32(addr);
850
851#ifdef CONFIG_PCIE1
852 SET_STD_PCIE_INFO(pci_info, 1);
853 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
854#else
855 setbits_be32(addr, _DEVDISR_PCIE1);
856#endif
857
858#ifdef CONFIG_PCIE2
859 SET_STD_PCIE_INFO(pci_info, 2);
860 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
861#else
862 setbits_be32(addr, _DEVDISR_PCIE2);
863#endif
864
865#ifdef CONFIG_PCIE3
866 SET_STD_PCIE_INFO(pci_info, 3);
867 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
868#else
869 setbits_be32(addr, _DEVDISR_PCIE3);
870#endif
871
872#ifdef CONFIG_PCIE4
873 SET_STD_PCIE_INFO(pci_info, 4);
874 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
875#else
876 setbits_be32(addr, _DEVDISR_PCIE4);
877#endif
878
879 return busno;
880}
881#else
882int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
883 struct fsl_pci_info *pci_info)
884{
885 return busno;
886}
887
888int fsl_pcie_init_board(int busno)
889{
890 return busno;
891}
892#endif
893
894#ifdef CONFIG_OF_BOARD_SETUP
895#include <linux/libfdt.h>
896#include <fdt_support.h>
897
898void ft_fsl_pci_setup(void *blob, const char *pci_compat,
899 unsigned long ctrl_addr)
900{
901 int off;
902 u32 bus_range[2];
903 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
904 struct pci_controller *hose;
905
906 hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
907
908
909 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
910 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
911
912 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
913
914 if (off < 0)
915 return;
916
917
918 if ((hose == NULL) || (hose->cfg_addr == NULL)) {
919 fdt_del_node(blob, off);
920 } else {
921 bus_range[0] = 0;
922 bus_range[1] = hose->last_busno - hose->first_busno;
923 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
924 fdt_pci_dma_ranges(blob, off, hose);
925 }
926}
927#endif
928
