1
2
3
4
5
6
7#include <common.h>
8#include <dm.h>
9#include <dm/device-internal.h>
10#include <dm/lists.h>
11#include <dm/pinctrl.h>
12#include <asm/io.h>
13#include <asm-generic/gpio.h>
14
15#include "pinctrl-mtk-common.h"
16
17#if CONFIG_IS_ENABLED(PINCONF)
18
19
20
21
22
23
24
25
26
27
28struct mtk_drive_desc {
29 u8 min;
30 u8 max;
31 u8 step;
32 u8 scal;
33};
34
35
36static const struct mtk_drive_desc mtk_drive[] = {
37 [DRV_GRP0] = { 4, 16, 4, 1 },
38 [DRV_GRP1] = { 4, 16, 4, 2 },
39 [DRV_GRP2] = { 2, 8, 2, 1 },
40 [DRV_GRP3] = { 2, 8, 2, 2 },
41 [DRV_GRP4] = { 2, 16, 2, 1 },
42};
43#endif
44
45static const char *mtk_pinctrl_dummy_name = "_dummy";
46
47static void mtk_w32(struct udevice *dev, u32 reg, u32 val)
48{
49 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
50
51 __raw_writel(val, priv->base + reg);
52}
53
54static u32 mtk_r32(struct udevice *dev, u32 reg)
55{
56 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
57
58 return __raw_readl(priv->base + reg);
59}
60
61static inline int get_count_order(unsigned int count)
62{
63 int order;
64
65 order = fls(count) - 1;
66 if (count & (count - 1))
67 order++;
68 return order;
69}
70
71void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set)
72{
73 u32 val;
74
75 val = mtk_r32(dev, reg);
76 val &= ~mask;
77 val |= set;
78 mtk_w32(dev, reg, val);
79}
80
81static int mtk_hw_pin_field_lookup(struct udevice *dev, int pin,
82 const struct mtk_pin_reg_calc *rc,
83 struct mtk_pin_field *pfd)
84{
85 const struct mtk_pin_field_calc *c, *e;
86 u32 bits;
87
88 c = rc->range;
89 e = c + rc->nranges;
90
91 while (c < e) {
92 if (pin >= c->s_pin && pin <= c->e_pin)
93 break;
94 c++;
95 }
96
97 if (c >= e)
98 return -EINVAL;
99
100
101
102
103
104 bits = c->fixed ? c->s_bit : c->s_bit + (pin - c->s_pin) * (c->x_bits);
105
106
107
108
109 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
110 pfd->bitpos = bits % c->sz_reg;
111 pfd->mask = (1 << c->x_bits) - 1;
112
113
114
115
116
117 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
118
119 return 0;
120}
121
122static int mtk_hw_pin_field_get(struct udevice *dev, int pin,
123 int field, struct mtk_pin_field *pfd)
124{
125 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
126 const struct mtk_pin_reg_calc *rc;
127
128 if (field < 0 || field >= PINCTRL_PIN_REG_MAX)
129 return -EINVAL;
130
131 if (priv->soc->reg_cal && priv->soc->reg_cal[field].range)
132 rc = &priv->soc->reg_cal[field];
133 else
134 return -EINVAL;
135
136 return mtk_hw_pin_field_lookup(dev, pin, rc, pfd);
137}
138
139static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
140{
141 *l = 32 - pf->bitpos;
142 *h = get_count_order(pf->mask) - *l;
143}
144
145static void mtk_hw_write_cross_field(struct udevice *dev,
146 struct mtk_pin_field *pf, int value)
147{
148 int nbits_l, nbits_h;
149
150 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
151
152 mtk_rmw(dev, pf->offset, pf->mask << pf->bitpos,
153 (value & pf->mask) << pf->bitpos);
154
155 mtk_rmw(dev, pf->offset + pf->next, BIT(nbits_h) - 1,
156 (value & pf->mask) >> nbits_l);
157}
158
159static void mtk_hw_read_cross_field(struct udevice *dev,
160 struct mtk_pin_field *pf, int *value)
161{
162 int nbits_l, nbits_h, h, l;
163
164 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
165
166 l = (mtk_r32(dev, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
167 h = (mtk_r32(dev, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
168
169 *value = (h << nbits_l) | l;
170}
171
172static int mtk_hw_set_value(struct udevice *dev, int pin, int field,
173 int value)
174{
175 struct mtk_pin_field pf;
176 int err;
177
178 err = mtk_hw_pin_field_get(dev, pin, field, &pf);
179 if (err)
180 return err;
181
182 if (!pf.next)
183 mtk_rmw(dev, pf.offset, pf.mask << pf.bitpos,
184 (value & pf.mask) << pf.bitpos);
185 else
186 mtk_hw_write_cross_field(dev, &pf, value);
187
188 return 0;
189}
190
191static int mtk_hw_get_value(struct udevice *dev, int pin, int field,
192 int *value)
193{
194 struct mtk_pin_field pf;
195 int err;
196
197 err = mtk_hw_pin_field_get(dev, pin, field, &pf);
198 if (err)
199 return err;
200
201 if (!pf.next)
202 *value = (mtk_r32(dev, pf.offset) >> pf.bitpos) & pf.mask;
203 else
204 mtk_hw_read_cross_field(dev, &pf, value);
205
206 return 0;
207}
208
209static int mtk_get_groups_count(struct udevice *dev)
210{
211 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
212
213 return priv->soc->ngrps;
214}
215
216static const char *mtk_get_pin_name(struct udevice *dev,
217 unsigned int selector)
218{
219 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
220
221 if (!priv->soc->grps[selector].name)
222 return mtk_pinctrl_dummy_name;
223
224 return priv->soc->pins[selector].name;
225}
226
227static int mtk_get_pins_count(struct udevice *dev)
228{
229 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
230
231 return priv->soc->npins;
232}
233
234static const char *mtk_get_group_name(struct udevice *dev,
235 unsigned int selector)
236{
237 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
238
239 if (!priv->soc->grps[selector].name)
240 return mtk_pinctrl_dummy_name;
241
242 return priv->soc->grps[selector].name;
243}
244
245static int mtk_get_functions_count(struct udevice *dev)
246{
247 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
248
249 return priv->soc->nfuncs;
250}
251
252static const char *mtk_get_function_name(struct udevice *dev,
253 unsigned int selector)
254{
255 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
256
257 if (!priv->soc->funcs[selector].name)
258 return mtk_pinctrl_dummy_name;
259
260 return priv->soc->funcs[selector].name;
261}
262
263static int mtk_pinmux_group_set(struct udevice *dev,
264 unsigned int group_selector,
265 unsigned int func_selector)
266{
267 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
268 const struct mtk_group_desc *grp =
269 &priv->soc->grps[group_selector];
270 int i;
271
272 for (i = 0; i < grp->num_pins; i++) {
273 int *pin_modes = grp->data;
274
275 mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,
276 pin_modes[i]);
277 }
278
279 return 0;
280}
281
282#if CONFIG_IS_ENABLED(PINCONF)
283static const struct pinconf_param mtk_conf_params[] = {
284 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
285 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
286 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
287 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
288 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
289 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
290 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
291 { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
292 { "output-high", PIN_CONFIG_OUTPUT, 1, },
293 { "output-low", PIN_CONFIG_OUTPUT, 0, },
294 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
295};
296
297int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
298{
299 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
300 const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
301 const struct mtk_drive_desc *tb;
302 int err = -ENOTSUPP;
303
304 tb = &mtk_drive[desc->drv_n];
305
306
307
308
309
310 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
311 arg = (arg / tb->step - 1) * tb->scal;
312
313 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg);
314 if (err)
315 return err;
316 }
317
318 return 0;
319}
320
321static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
322 unsigned int param, unsigned int arg)
323{
324 int err = 0;
325
326 switch (param) {
327 case PIN_CONFIG_BIAS_DISABLE:
328 case PIN_CONFIG_BIAS_PULL_UP:
329 case PIN_CONFIG_BIAS_PULL_DOWN:
330 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
331 (param == PIN_CONFIG_BIAS_PULL_UP) ? 3 : 2;
332
333 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL,
334 arg & 1);
335 if (err)
336 goto err;
337
338 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN,
339 !!(arg & 2));
340 if (err)
341 goto err;
342 break;
343 case PIN_CONFIG_OUTPUT_ENABLE:
344 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT, 0);
345 if (err)
346 goto err;
347 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
348 if (err)
349 goto err;
350 break;
351 case PIN_CONFIG_INPUT_ENABLE:
352 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1);
353 if (err)
354 goto err;
355 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
356 if (err)
357 goto err;
358 break;
359 case PIN_CONFIG_OUTPUT:
360 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
361 if (err)
362 goto err;
363
364 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DO, arg);
365 if (err)
366 goto err;
367 break;
368 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
369
370
371
372 arg = arg ? 2 : 1;
373 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR,
374 arg & 1);
375 if (err)
376 goto err;
377
378 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT,
379 !!(arg & 2));
380 if (err)
381 goto err;
382 break;
383 case PIN_CONFIG_DRIVE_STRENGTH:
384 err = mtk_pinconf_drive_set(dev, pin, arg);
385 if (err)
386 goto err;
387 break;
388
389 default:
390 err = -ENOTSUPP;
391 }
392
393err:
394
395 return err;
396}
397
398static int mtk_pinconf_group_set(struct udevice *dev,
399 unsigned int group_selector,
400 unsigned int param, unsigned int arg)
401{
402 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
403 const struct mtk_group_desc *grp =
404 &priv->soc->grps[group_selector];
405 int i, ret;
406
407 for (i = 0; i < grp->num_pins; i++) {
408 ret = mtk_pinconf_set(dev, grp->pins[i], param, arg);
409 if (ret)
410 return ret;
411 }
412
413 return 0;
414}
415#endif
416
417const struct pinctrl_ops mtk_pinctrl_ops = {
418 .get_pins_count = mtk_get_pins_count,
419 .get_pin_name = mtk_get_pin_name,
420 .get_groups_count = mtk_get_groups_count,
421 .get_group_name = mtk_get_group_name,
422 .get_functions_count = mtk_get_functions_count,
423 .get_function_name = mtk_get_function_name,
424 .pinmux_group_set = mtk_pinmux_group_set,
425#if CONFIG_IS_ENABLED(PINCONF)
426 .pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
427 .pinconf_params = mtk_conf_params,
428 .pinconf_set = mtk_pinconf_set,
429 .pinconf_group_set = mtk_pinconf_group_set,
430#endif
431 .set_state = pinctrl_generic_set_state,
432};
433
434static int mtk_gpio_get(struct udevice *dev, unsigned int off)
435{
436 int val, err;
437
438 err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DI, &val);
439 if (err)
440 return err;
441
442 return !!val;
443}
444
445static int mtk_gpio_set(struct udevice *dev, unsigned int off, int val)
446{
447 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DO, !!val);
448}
449
450static int mtk_gpio_get_direction(struct udevice *dev, unsigned int off)
451{
452 int val, err;
453
454 err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DIR, &val);
455 if (err)
456 return err;
457
458 return val ? GPIOF_OUTPUT : GPIOF_INPUT;
459}
460
461static int mtk_gpio_direction_input(struct udevice *dev, unsigned int off)
462{
463 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 0);
464}
465
466static int mtk_gpio_direction_output(struct udevice *dev,
467 unsigned int off, int val)
468{
469 mtk_gpio_set(dev, off, val);
470
471
472 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 1);
473}
474
475static int mtk_gpio_request(struct udevice *dev, unsigned int off,
476 const char *label)
477{
478 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, 0);
479}
480
481static int mtk_gpio_probe(struct udevice *dev)
482{
483 struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
484 struct gpio_dev_priv *uc_priv;
485
486 uc_priv = dev_get_uclass_priv(dev);
487 uc_priv->bank_name = priv->soc->name;
488 uc_priv->gpio_count = priv->soc->npins;
489
490 return 0;
491}
492
493static const struct dm_gpio_ops mtk_gpio_ops = {
494 .request = mtk_gpio_request,
495 .set_value = mtk_gpio_set,
496 .get_value = mtk_gpio_get,
497 .get_function = mtk_gpio_get_direction,
498 .direction_input = mtk_gpio_direction_input,
499 .direction_output = mtk_gpio_direction_output,
500};
501
502static struct driver mtk_gpio_driver = {
503 .name = "mediatek_gpio",
504 .id = UCLASS_GPIO,
505 .probe = mtk_gpio_probe,
506 .ops = &mtk_gpio_ops,
507};
508
509static int mtk_gpiochip_register(struct udevice *parent)
510{
511 struct uclass_driver *drv;
512 struct udevice *dev;
513 int ret;
514 ofnode node;
515
516 drv = lists_uclass_lookup(UCLASS_GPIO);
517 if (!drv)
518 return -ENOENT;
519
520 dev_for_each_subnode(node, parent)
521 if (ofnode_read_bool(node, "gpio-controller")) {
522 ret = 0;
523 break;
524 }
525
526 if (ret)
527 return ret;
528
529 ret = device_bind_with_driver_data(parent, &mtk_gpio_driver,
530 "mediatek_gpio", 0, node,
531 &dev);
532 if (ret)
533 return ret;
534
535 return 0;
536}
537
538int mtk_pinctrl_common_probe(struct udevice *dev,
539 struct mtk_pinctrl_soc *soc)
540{
541 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
542 int ret;
543
544 priv->base = dev_read_addr_ptr(dev);
545 if (priv->base == (void *)FDT_ADDR_T_NONE)
546 return -EINVAL;
547
548 priv->soc = soc;
549
550 ret = mtk_gpiochip_register(dev);
551 if (ret)
552 return ret;
553
554 return 0;
555}
556
