LXR uboot/drivers/spi/davinci

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   4 *
   5 * Driver for SPI controller on DaVinci. Based on atmel_spi.c
   6 * by Atmel Corporation
   7 *
   8 * Copyright (C) 2007 Atmel Corporation
   9 */
  10
  11#include <common.h>
  12#include <spi.h>
  13#include <malloc.h>
  14#include <asm/io.h>
  15#include <asm/arch/hardware.h>
  16#include <dm.h>
  17#include <dm/platform_data/spi_davinci.h>
  18
  19/* SPIGCR0 */
  20#define SPIGCR0_SPIENA_MASK     0x1
  21#define SPIGCR0_SPIRST_MASK     0x0
  22
  23/* SPIGCR0 */
  24#define SPIGCR1_CLKMOD_MASK     BIT(1)
  25#define SPIGCR1_MASTER_MASK     BIT(0)
  26#define SPIGCR1_SPIENA_MASK     BIT(24)
  27
  28/* SPIPC0 */
  29#define SPIPC0_DIFUN_MASK       BIT(11)         /* SIMO */
  30#define SPIPC0_DOFUN_MASK       BIT(10)         /* SOMI */
  31#define SPIPC0_CLKFUN_MASK      BIT(9)          /* CLK */
  32#define SPIPC0_EN0FUN_MASK      BIT(0)
  33
  34/* SPIFMT0 */
  35#define SPIFMT_SHIFTDIR_SHIFT   20
  36#define SPIFMT_POLARITY_SHIFT   17
  37#define SPIFMT_PHASE_SHIFT      16
  38#define SPIFMT_PRESCALE_SHIFT   8
  39
  40/* SPIDAT1 */
  41#define SPIDAT1_CSHOLD_SHIFT    28
  42#define SPIDAT1_CSNR_SHIFT      16
  43
  44/* SPIDELAY */
  45#define SPI_C2TDELAY_SHIFT      24
  46#define SPI_T2CDELAY_SHIFT      16
  47
  48/* SPIBUF */
  49#define SPIBUF_RXEMPTY_MASK     BIT(31)
  50#define SPIBUF_TXFULL_MASK      BIT(29)
  51
  52/* SPIDEF */
  53#define SPIDEF_CSDEF0_MASK      BIT(0)
  54
  55#ifndef CONFIG_DM_SPI
  56#define SPI0_BUS                0
  57#define SPI0_BASE               CONFIG_SYS_SPI_BASE
  58/*
  59 * Define default SPI0_NUM_CS as 1 for existing platforms that uses this
  60 * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
  61 * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
  62 */
  63#ifndef CONFIG_SYS_SPI0
  64#define SPI0_NUM_CS             1
  65#else
  66#define SPI0_NUM_CS             CONFIG_SYS_SPI0_NUM_CS
  67#endif
  68
  69/*
  70 * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
  71 * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
  72 */
  73#ifdef CONFIG_SYS_SPI1
  74#define SPI1_BUS                1
  75#define SPI1_NUM_CS             CONFIG_SYS_SPI1_NUM_CS
  76#define SPI1_BASE               CONFIG_SYS_SPI1_BASE
  77#endif
  78
  79/*
  80 * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
  81 * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
  82 */
  83#ifdef CONFIG_SYS_SPI2
  84#define SPI2_BUS                2
  85#define SPI2_NUM_CS             CONFIG_SYS_SPI2_NUM_CS
  86#define SPI2_BASE               CONFIG_SYS_SPI2_BASE
  87#endif
  88#endif
  89
  90DECLARE_GLOBAL_DATA_PTR;
  91
  92/* davinci spi register set */
  93struct davinci_spi_regs {
  94        dv_reg  gcr0;           /* 0x00 */
  95        dv_reg  gcr1;           /* 0x04 */
  96        dv_reg  int0;           /* 0x08 */
  97        dv_reg  lvl;            /* 0x0c */
  98        dv_reg  flg;            /* 0x10 */
  99        dv_reg  pc0;            /* 0x14 */
 100        dv_reg  pc1;            /* 0x18 */
 101        dv_reg  pc2;            /* 0x1c */
 102        dv_reg  pc3;            /* 0x20 */
 103        dv_reg  pc4;            /* 0x24 */
 104        dv_reg  pc5;            /* 0x28 */
 105        dv_reg  rsvd[3];
 106        dv_reg  dat0;           /* 0x38 */
 107        dv_reg  dat1;           /* 0x3c */
 108        dv_reg  buf;            /* 0x40 */
 109        dv_reg  emu;            /* 0x44 */
 110        dv_reg  delay;          /* 0x48 */
 111        dv_reg  def;            /* 0x4c */
 112        dv_reg  fmt0;           /* 0x50 */
 113        dv_reg  fmt1;           /* 0x54 */
 114        dv_reg  fmt2;           /* 0x58 */
 115        dv_reg  fmt3;           /* 0x5c */
 116        dv_reg  intvec0;        /* 0x60 */
 117        dv_reg  intvec1;        /* 0x64 */
 118};
 119
 120/* davinci spi slave */
 121struct davinci_spi_slave {
 122#ifndef CONFIG_DM_SPI
 123        struct spi_slave slave;
 124#endif
 125        struct davinci_spi_regs *regs;
 126        unsigned int freq; /* current SPI bus frequency */
 127        unsigned int mode; /* current SPI mode used */
 128        u8 num_cs;         /* total no. of CS available */
 129        u8 cur_cs;         /* CS of current slave */
 130        bool half_duplex;  /* true, if master is half-duplex only */
 131};
 132
 133/*
 134 * This functions needs to act like a macro to avoid pipeline reloads in the
 135 * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
 136 * appears to be zero bytes (da830).
 137 */
 138__attribute__((always_inline))
 139static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
 140{
 141        u32     buf_reg_val;
 142
 143        /* send out data */
 144        writel(data, &ds->regs->dat1);
 145
 146        /* wait for the data to clock in/out */
 147        while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
 148                ;
 149
 150        return buf_reg_val;
 151}
 152
 153static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len,
 154                            u8 *rxp, unsigned long flags)
 155{
 156        unsigned int data1_reg_val;
 157
 158        /* enable CS hold, CS[n] and clear the data bits */
 159        data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
 160                         (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
 161
 162        /* wait till TXFULL is deasserted */
 163        while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
 164                ;
 165
 166        /* preload the TX buffer to avoid clock starvation */
 167        writel(data1_reg_val, &ds->regs->dat1);
 168
 169        /* keep reading 1 byte until only 1 byte left */
 170        while ((len--) > 1)
 171                *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
 172
 173        /* clear CS hold when we reach the end */
 174        if (flags & SPI_XFER_END)
 175                data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
 176
 177        /* read the last byte */
 178        *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
 179
 180        return 0;
 181}
 182
 183static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len,
 184                             const u8 *txp, unsigned long flags)
 185{
 186        unsigned int data1_reg_val;
 187
 188        /* enable CS hold and clear the data bits */
 189        data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
 190                         (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
 191
 192        /* wait till TXFULL is deasserted */
 193        while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
 194                ;
 195
 196        /* preload the TX buffer to avoid clock starvation */
 197        if (len > 2) {
 198                writel(data1_reg_val | *txp++, &ds->regs->dat1);
 199                len--;
 200        }
 201
 202        /* keep writing 1 byte until only 1 byte left */
 203        while ((len--) > 1)
 204                davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
 205
 206        /* clear CS hold when we reach the end */
 207        if (flags & SPI_XFER_END)
 208                data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
 209
 210        /* write the last byte */
 211        davinci_spi_xfer_data(ds, data1_reg_val | *txp);
 212
 213        return 0;
 214}
 215
 216static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
 217                                  int len, u8 *rxp, const u8 *txp,
 218                                  unsigned long flags)
 219{
 220        unsigned int data1_reg_val;
 221
 222        /* enable CS hold and clear the data bits */
 223        data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
 224                         (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
 225
 226        /* wait till TXFULL is deasserted */
 227        while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
 228                ;
 229
 230        /* keep reading and writing 1 byte until only 1 byte left */
 231        while ((len--) > 1)
 232                *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
 233
 234        /* clear CS hold when we reach the end */
 235        if (flags & SPI_XFER_END)
 236                data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
 237
 238        /* read and write the last byte */
 239        *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
 240
 241        return 0;
 242}
 243
 244
 245static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
 246{
 247        unsigned int mode = 0, scalar;
 248
 249        /* Enable the SPI hardware */
 250        writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
 251        udelay(1000);
 252        writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
 253
 254        /* Set master mode, powered up and not activated */
 255        writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
 256
 257        /* CS, CLK, SIMO and SOMI are functional pins */
 258        writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
 259                SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
 260
 261        /* setup format */
 262        scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
 263
 264        /*
 265         * Use following format:
 266         *   character length = 8,
 267         *   MSB shifted out first
 268         */
 269        if (ds->mode & SPI_CPOL)
 270                mode |= SPI_CPOL;
 271        if (!(ds->mode & SPI_CPHA))
 272                mode |= SPI_CPHA;
 273        writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
 274                (mode << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
 275
 276        /*
 277         * Including a minor delay. No science here. Should be good even with
 278         * no delay
 279         */
 280        writel((50 << SPI_C2TDELAY_SHIFT) |
 281                (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
 282
 283        /* default chip select register */
 284        writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
 285
 286        /* no interrupts */
 287        writel(0, &ds->regs->int0);
 288        writel(0, &ds->regs->lvl);
 289
 290        /* enable SPI */
 291        writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
 292
 293        return 0;
 294}
 295
 296static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
 297{
 298        /* Disable the SPI hardware */
 299        writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
 300
 301        return 0;
 302}
 303
 304static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
 305                unsigned int bitlen,  const void *dout, void *din,
 306                unsigned long flags)
 307{
 308        unsigned int len;
 309
 310        if (bitlen == 0)
 311                /* Finish any previously submitted transfers */
 312                goto out;
 313
 314        /*
 315         * It's not clear how non-8-bit-aligned transfers are supposed to be
 316         * represented as a stream of bytes...this is a limitation of
 317         * the current SPI interface - here we terminate on receiving such a
 318         * transfer request.
 319         */
 320        if (bitlen % 8) {
 321                /* Errors always terminate an ongoing transfer */
 322                flags |= SPI_XFER_END;
 323                goto out;
 324        }
 325
 326        len = bitlen / 8;
 327
 328        if (!dout)
 329                return davinci_spi_read(ds, len, din, flags);
 330        if (!din)
 331                return davinci_spi_write(ds, len, dout, flags);
 332        if (!ds->half_duplex)
 333                return davinci_spi_read_write(ds, len, din, dout, flags);
 334
 335        printf("SPI full duplex not supported\n");
 336        flags |= SPI_XFER_END;
 337
 338out:
 339        if (flags & SPI_XFER_END) {
 340                u8 dummy = 0;
 341                davinci_spi_write(ds, 1, &dummy, flags);
 342        }
 343        return 0;
 344}
 345
 346#ifndef CONFIG_DM_SPI
 347
 348static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
 349{
 350        return container_of(slave, struct davinci_spi_slave, slave);
 351}
 352
 353int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 354{
 355        int ret = 0;
 356
 357        switch (bus) {
 358        case SPI0_BUS:
 359                if (cs < SPI0_NUM_CS)
 360                        ret = 1;
 361                break;
 362#ifdef CONFIG_SYS_SPI1
 363        case SPI1_BUS:
 364                if (cs < SPI1_NUM_CS)
 365                        ret = 1;
 366                break;
 367#endif
 368#ifdef CONFIG_SYS_SPI2
 369        case SPI2_BUS:
 370                if (cs < SPI2_NUM_CS)
 371                        ret = 1;
 372                break;
 373#endif
 374        default:
 375                /* Invalid bus number. Do nothing */
 376                break;
 377        }
 378        return ret;
 379}
 380
 381void spi_cs_activate(struct spi_slave *slave)
 382{
 383        /* do nothing */
 384}
 385
 386void spi_cs_deactivate(struct spi_slave *slave)
 387{
 388        /* do nothing */
 389}
 390
 391struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 392                        unsigned int max_hz, unsigned int mode)
 393{
 394        struct davinci_spi_slave        *ds;
 395
 396        if (!spi_cs_is_valid(bus, cs))
 397                return NULL;
 398
 399        ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
 400        if (!ds)
 401                return NULL;
 402
 403        switch (bus) {
 404        case SPI0_BUS:
 405                ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
 406                break;
 407#ifdef CONFIG_SYS_SPI1
 408        case SPI1_BUS:
 409                ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
 410                break;
 411#endif
 412#ifdef CONFIG_SYS_SPI2
 413        case SPI2_BUS:
 414                ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
 415                break;
 416#endif
 417        default: /* Invalid bus number */
 418                return NULL;
 419        }
 420
 421        ds->freq = max_hz;
 422        ds->mode = mode;
 423
 424        return &ds->slave;
 425}
 426
 427void spi_free_slave(struct spi_slave *slave)
 428{
 429        struct davinci_spi_slave *ds = to_davinci_spi(slave);
 430
 431        free(ds);
 432}
 433
 434int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 435             const void *dout, void *din, unsigned long flags)
 436{
 437        struct davinci_spi_slave *ds = to_davinci_spi(slave);
 438
 439        ds->cur_cs = slave->cs;
 440
 441        return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
 442}
 443
 444int spi_claim_bus(struct spi_slave *slave)
 445{
 446        struct davinci_spi_slave *ds = to_davinci_spi(slave);
 447
 448#ifdef CONFIG_SPI_HALF_DUPLEX
 449        ds->half_duplex = true;
 450#else
 451        ds->half_duplex = false;
 452#endif
 453        return __davinci_spi_claim_bus(ds, ds->slave.cs);
 454}
 455
 456void spi_release_bus(struct spi_slave *slave)
 457{
 458        struct davinci_spi_slave *ds = to_davinci_spi(slave);
 459
 460        __davinci_spi_release_bus(ds);
 461}
 462
 463#else
 464static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
 465{
 466        struct davinci_spi_slave *ds = dev_get_priv(bus);
 467
 468        debug("%s speed %u\n", __func__, max_hz);
 469        if (max_hz > CONFIG_SYS_SPI_CLK / 2)
 470                return -EINVAL;
 471
 472        ds->freq = max_hz;
 473
 474        return 0;
 475}
 476
 477static int davinci_spi_set_mode(struct udevice *bus, uint mode)
 478{
 479        struct davinci_spi_slave *ds = dev_get_priv(bus);
 480
 481        debug("%s mode %u\n", __func__, mode);
 482        ds->mode = mode;
 483
 484        return 0;
 485}
 486
 487static int davinci_spi_claim_bus(struct udevice *dev)
 488{
 489        struct dm_spi_slave_platdata *slave_plat =
 490                dev_get_parent_platdata(dev);
 491        struct udevice *bus = dev->parent;
 492        struct davinci_spi_slave *ds = dev_get_priv(bus);
 493
 494        if (slave_plat->cs >= ds->num_cs) {
 495                printf("Invalid SPI chipselect\n");
 496                return -EINVAL;
 497        }
 498        ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
 499
 500        return __davinci_spi_claim_bus(ds, slave_plat->cs);
 501}
 502
 503static int davinci_spi_release_bus(struct udevice *dev)
 504{
 505        struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
 506
 507        return __davinci_spi_release_bus(ds);
 508}
 509
 510static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
 511                            const void *dout, void *din,
 512                            unsigned long flags)
 513{
 514        struct dm_spi_slave_platdata *slave =
 515                dev_get_parent_platdata(dev);
 516        struct udevice *bus = dev->parent;
 517        struct davinci_spi_slave *ds = dev_get_priv(bus);
 518
 519        if (slave->cs >= ds->num_cs) {
 520                printf("Invalid SPI chipselect\n");
 521                return -EINVAL;
 522        }
 523        ds->cur_cs = slave->cs;
 524
 525        return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
 526}
 527
 528static const struct dm_spi_ops davinci_spi_ops = {
 529        .claim_bus      = davinci_spi_claim_bus,
 530        .release_bus    = davinci_spi_release_bus,
 531        .xfer           = davinci_spi_xfer,
 532        .set_speed      = davinci_spi_set_speed,
 533        .set_mode       = davinci_spi_set_mode,
 534};
 535
 536static int davinci_spi_probe(struct udevice *bus)
 537{
 538        struct davinci_spi_slave *ds = dev_get_priv(bus);
 539        struct davinci_spi_platdata *plat = bus->platdata;
 540        ds->regs = plat->regs;
 541        ds->num_cs = plat->num_cs;
 542
 543        return 0;
 544}
 545
 546#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 547static int davinci_ofdata_to_platadata(struct udevice *bus)
 548{
 549        struct davinci_spi_platdata *plat = bus->platdata;
 550        fdt_addr_t addr;
 551
 552        addr = devfdt_get_addr(bus);
 553        if (addr == FDT_ADDR_T_NONE)
 554                return -EINVAL;
 555
 556        plat->regs = (struct davinci_spi_regs *)addr;
 557        plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "num-cs", 4);
 558
 559        return 0;
 560}
 561
 562static const struct udevice_id davinci_spi_ids[] = {
 563        { .compatible = "ti,keystone-spi" },
 564        { .compatible = "ti,dm6441-spi" },
 565        { .compatible = "ti,da830-spi" },
 566        { }
 567};
 568#endif
 569
 570U_BOOT_DRIVER(davinci_spi) = {
 571        .name = "davinci_spi",
 572        .id = UCLASS_SPI,
 573#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 574        .of_match = davinci_spi_ids,
 575        .ofdata_to_platdata = davinci_ofdata_to_platadata,
 576        .platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata),
 577#endif
 578        .probe = davinci_spi_probe,
 579        .ops = &davinci_spi_ops,
 580        .priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
 581};
 582#endif
 583