LXR uboot/drivers/video/mxsfb.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Freescale i.MX23/i.MX28 LCDIF driver
   4 *
   5 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
   6 */
   7#include <common.h>
   8#include <dm.h>
   9#include <env.h>
  10#include <linux/errno.h>
  11#include <malloc.h>
  12#include <video.h>
  13#include <video_fb.h>
  14
  15#include <asm/arch/clock.h>
  16#include <asm/arch/imx-regs.h>
  17#include <asm/arch/sys_proto.h>
  18#include <asm/mach-imx/dma.h>
  19#include <asm/io.h>
  20
  21#include "videomodes.h"
  22
  23#define PS2KHZ(ps)      (1000000000UL / (ps))
  24#define HZ2PS(hz)       (1000000000UL / ((hz) / 1000))
  25
  26#define BITS_PP         18
  27#define BYTES_PP        4
  28
  29struct mxs_dma_desc desc;
  30
  31/**
  32 * mxsfb_system_setup() - Fine-tune LCDIF configuration
  33 *
  34 * This function is used to adjust the LCDIF configuration. This is usually
  35 * needed when driving the controller in System-Mode to operate an 8080 or
  36 * 6800 connected SmartLCD.
  37 */
  38__weak void mxsfb_system_setup(void)
  39{
  40}
  41
  42/*
  43 * ARIES M28EVK:
  44 * setenv videomode
  45 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  46 *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  47 *
  48 * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  49 * setenv videomode
  50 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  51 *       le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  52 */
  53
  54static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
  55{
  56        struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  57        uint32_t word_len = 0, bus_width = 0;
  58        uint8_t valid_data = 0;
  59
  60        /* Kick in the LCDIF clock */
  61        mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
  62
  63        /* Restart the LCDIF block */
  64        mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  65
  66        switch (bpp) {
  67        case 24:
  68                word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  69                bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
  70                valid_data = 0x7;
  71                break;
  72        case 18:
  73                word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  74                bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
  75                valid_data = 0x7;
  76                break;
  77        case 16:
  78                word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
  79                bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
  80                valid_data = 0xf;
  81                break;
  82        case 8:
  83                word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
  84                bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
  85                valid_data = 0xf;
  86                break;
  87        }
  88
  89        writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
  90                LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
  91                &regs->hw_lcdif_ctrl);
  92
  93        writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
  94                &regs->hw_lcdif_ctrl1);
  95
  96        mxsfb_system_setup();
  97
  98        writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
  99                &regs->hw_lcdif_transfer_count);
 100
 101        writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
 102                LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
 103                LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 104                mode->vsync_len, &regs->hw_lcdif_vdctrl0);
 105        writel(mode->upper_margin + mode->lower_margin +
 106                mode->vsync_len + mode->yres,
 107                &regs->hw_lcdif_vdctrl1);
 108        writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
 109                (mode->left_margin + mode->right_margin +
 110                mode->hsync_len + mode->xres),
 111                &regs->hw_lcdif_vdctrl2);
 112        writel(((mode->left_margin + mode->hsync_len) <<
 113                LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
 114                (mode->upper_margin + mode->vsync_len),
 115                &regs->hw_lcdif_vdctrl3);
 116        writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
 117                &regs->hw_lcdif_vdctrl4);
 118
 119        writel(fb_addr, &regs->hw_lcdif_cur_buf);
 120        writel(fb_addr, &regs->hw_lcdif_next_buf);
 121
 122        /* Flush FIFO first */
 123        writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
 124
 125#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
 126        /* Sync signals ON */
 127        setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
 128#endif
 129
 130        /* FIFO cleared */
 131        writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
 132
 133        /* RUN! */
 134        writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 135}
 136
 137static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, u32 fb)
 138{
 139        /* Start framebuffer */
 140        mxs_lcd_init(fb, mode, bpp);
 141
 142#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
 143        /*
 144         * If the LCD runs in system mode, the LCD refresh has to be triggered
 145         * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
 146         * having to set this bit manually after every single change in the
 147         * framebuffer memory, we set up specially crafted circular DMA, which
 148         * sets the RUN bit, then waits until it gets cleared and repeats this
 149         * infinitelly. This way, we get smooth continuous updates of the LCD.
 150         */
 151        struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 152
 153        memset(&desc, 0, sizeof(struct mxs_dma_desc));
 154        desc.address = (dma_addr_t)&desc;
 155        desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
 156                        MXS_DMA_DESC_WAIT4END |
 157                        (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
 158        desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
 159        desc.cmd.next = (uint32_t)&desc.cmd;
 160
 161        /* Execute the DMA chain. */
 162        mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
 163#endif
 164
 165        return 0;
 166}
 167
 168static int mxs_remove_common(u32 fb)
 169{
 170        struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 171        int timeout = 1000000;
 172
 173        if (!fb)
 174                return -EINVAL;
 175
 176        writel(fb, &regs->hw_lcdif_cur_buf_reg);
 177        writel(fb, &regs->hw_lcdif_next_buf_reg);
 178        writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
 179        while (--timeout) {
 180                if (readl(&regs->hw_lcdif_ctrl1_reg) &
 181                    LCDIF_CTRL1_VSYNC_EDGE_IRQ)
 182                        break;
 183                udelay(1);
 184        }
 185        mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
 186
 187        return 0;
 188}
 189
 190#ifndef CONFIG_DM_VIDEO
 191
 192static GraphicDevice panel;
 193
 194void lcdif_power_down(void)
 195{
 196        mxs_remove_common(panel.frameAdrs);
 197}
 198
 199void *video_hw_init(void)
 200{
 201        int bpp = -1;
 202        int ret = 0;
 203        char *penv;
 204        void *fb = NULL;
 205        struct ctfb_res_modes mode;
 206
 207        puts("Video: ");
 208
 209        /* Suck display configuration from "videomode" variable */
 210        penv = env_get("videomode");
 211        if (!penv) {
 212                puts("MXSFB: 'videomode' variable not set!\n");
 213                return NULL;
 214        }
 215
 216        bpp = video_get_params(&mode, penv);
 217
 218        /* fill in Graphic device struct */
 219        sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
 220
 221        panel.winSizeX = mode.xres;
 222        panel.winSizeY = mode.yres;
 223        panel.plnSizeX = mode.xres;
 224        panel.plnSizeY = mode.yres;
 225
 226        switch (bpp) {
 227        case 24:
 228        case 18:
 229                panel.gdfBytesPP = 4;
 230                panel.gdfIndex = GDF_32BIT_X888RGB;
 231                break;
 232        case 16:
 233                panel.gdfBytesPP = 2;
 234                panel.gdfIndex = GDF_16BIT_565RGB;
 235                break;
 236        case 8:
 237                panel.gdfBytesPP = 1;
 238                panel.gdfIndex = GDF__8BIT_INDEX;
 239                break;
 240        default:
 241                printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
 242                return NULL;
 243        }
 244
 245        panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
 246
 247        /* Allocate framebuffer */
 248        fb = memalign(ARCH_DMA_MINALIGN,
 249                      roundup(panel.memSize, ARCH_DMA_MINALIGN));
 250        if (!fb) {
 251                printf("MXSFB: Error allocating framebuffer!\n");
 252                return NULL;
 253        }
 254
 255        /* Wipe framebuffer */
 256        memset(fb, 0, panel.memSize);
 257
 258        panel.frameAdrs = (u32)fb;
 259
 260        printf("%s\n", panel.modeIdent);
 261
 262        ret = mxs_probe_common(&mode, bpp, (u32)fb);
 263        if (ret)
 264                goto dealloc_fb;
 265
 266        return (void *)&panel;
 267
 268dealloc_fb:
 269        free(fb);
 270
 271        return NULL;
 272}
 273#else /* ifndef CONFIG_DM_VIDEO */
 274
 275static int mxs_of_get_timings(struct udevice *dev,
 276                              struct display_timing *timings,
 277                              u32 *bpp)
 278{
 279        int ret = 0;
 280        u32 display_phandle;
 281        ofnode display_node;
 282
 283        ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
 284        if (ret) {
 285                dev_err(dev, "required display property isn't provided\n");
 286                return -EINVAL;
 287        }
 288
 289        display_node = ofnode_get_by_phandle(display_phandle);
 290        if (!ofnode_valid(display_node)) {
 291                dev_err(dev, "failed to find display subnode\n");
 292                return -EINVAL;
 293        }
 294
 295        ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
 296        if (ret) {
 297                dev_err(dev,
 298                        "required bits-per-pixel property isn't provided\n");
 299                return -EINVAL;
 300        }
 301
 302        ret = ofnode_decode_display_timing(display_node, 0, timings);
 303        if (ret) {
 304                dev_err(dev, "failed to get any display timings\n");
 305                return -EINVAL;
 306        }
 307
 308        return ret;
 309}
 310
 311static int mxs_video_probe(struct udevice *dev)
 312{
 313        struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 314        struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 315
 316        struct ctfb_res_modes mode;
 317        struct display_timing timings;
 318        u32 bpp = 0;
 319        u32 fb_start, fb_end;
 320        int ret;
 321
 322        debug("%s() plat: base 0x%lx, size 0x%x\n",
 323               __func__, plat->base, plat->size);
 324
 325        ret = mxs_of_get_timings(dev, &timings, &bpp);
 326        if (ret)
 327                return ret;
 328
 329        mode.xres = timings.hactive.typ;
 330        mode.yres = timings.vactive.typ;
 331        mode.left_margin = timings.hback_porch.typ;
 332        mode.right_margin = timings.hfront_porch.typ;
 333        mode.upper_margin = timings.vback_porch.typ;
 334        mode.lower_margin = timings.vfront_porch.typ;
 335        mode.hsync_len = timings.hsync_len.typ;
 336        mode.vsync_len = timings.vsync_len.typ;
 337        mode.pixclock = HZ2PS(timings.pixelclock.typ);
 338
 339        ret = mxs_probe_common(&mode, bpp, plat->base);
 340        if (ret)
 341                return ret;
 342
 343        switch (bpp) {
 344        case 32:
 345        case 24:
 346        case 18:
 347                uc_priv->bpix = VIDEO_BPP32;
 348                break;
 349        case 16:
 350                uc_priv->bpix = VIDEO_BPP16;
 351                break;
 352        case 8:
 353                uc_priv->bpix = VIDEO_BPP8;
 354                break;
 355        default:
 356                dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 357                return -EINVAL;
 358        }
 359
 360        uc_priv->xsize = mode.xres;
 361        uc_priv->ysize = mode.yres;
 362
 363        /* Enable dcache for the frame buffer */
 364        fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
 365        fb_end = plat->base + plat->size;
 366        fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
 367        mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
 368                                        DCACHE_WRITEBACK);
 369        video_set_flush_dcache(dev, true);
 370        gd->fb_base = plat->base;
 371
 372        return ret;
 373}
 374
 375static int mxs_video_bind(struct udevice *dev)
 376{
 377        struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 378        struct display_timing timings;
 379        u32 bpp = 0;
 380        u32 bytes_pp = 0;
 381        int ret;
 382
 383        ret = mxs_of_get_timings(dev, &timings, &bpp);
 384        if (ret)
 385                return ret;
 386
 387        switch (bpp) {
 388        case 32:
 389        case 24:
 390        case 18:
 391                bytes_pp = 4;
 392                break;
 393        case 16:
 394                bytes_pp = 2;
 395                break;
 396        case 8:
 397                bytes_pp = 1;
 398                break;
 399        default:
 400                dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 401                return -EINVAL;
 402        }
 403
 404        plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
 405
 406        return 0;
 407}
 408
 409static int mxs_video_remove(struct udevice *dev)
 410{
 411        struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 412
 413        mxs_remove_common(plat->base);
 414
 415        return 0;
 416}
 417
 418static const struct udevice_id mxs_video_ids[] = {
 419        { .compatible = "fsl,imx23-lcdif" },
 420        { .compatible = "fsl,imx28-lcdif" },
 421        { .compatible = "fsl,imx7ulp-lcdif" },
 422        { /* sentinel */ }
 423};
 424
 425U_BOOT_DRIVER(mxs_video) = {
 426        .name   = "mxs_video",
 427        .id     = UCLASS_VIDEO,
 428        .of_match = mxs_video_ids,
 429        .bind   = mxs_video_bind,
 430        .probe  = mxs_video_probe,
 431        .remove = mxs_video_remove,
 432        .flags  = DM_FLAG_PRE_RELOC,
 433};
 434#endif /* ifndef CONFIG_DM_VIDEO */
 435