LXR uboot/include/configs/MPC8349ITX.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4 */
   5
   6/*
   7 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
   8
   9 Memory map:
  10
  11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  17 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  18 0xF001_0000-0xF001_FFFF Local bus expansion slot
  19 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  21 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  22
  23 I2C address list:
  24                                                Align.  Board
  25 Bus    Addr    Part No.        Description     Length  Location
  26 ----------------------------------------------------------------
  27 I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
  28
  29 I2C1   0x20    PCF8574         I2C Expander    0       U8
  30 I2C1   0x21    PCF8574         I2C Expander    0       U10
  31 I2C1   0x38    PCF8574A        I2C Expander    0       U8
  32 I2C1   0x39    PCF8574A        I2C Expander    0       U10
  33 I2C1   0x51    (DDR)           DDR EEPROM      1       U1
  34 I2C1   0x68    DS1339          RTC             1       U68
  35
  36 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  37*/
  38
  39#ifndef __CONFIG_H
  40#define __CONFIG_H
  41
  42#define CONFIG_MISC_INIT_F
  43
  44/*
  45 * On-board devices
  46 */
  47
  48#ifdef CONFIG_TARGET_MPC8349ITX
  49/* The CF card interface on the back of the board */
  50#define CONFIG_COMPACT_FLASH
  51#define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
  52#define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
  53#endif
  54
  55#define CONFIG_RTC_DS1337
  56#define CONFIG_SYS_I2C
  57
  58/*
  59 * Device configurations
  60 */
  61
  62/* I2C */
  63#ifdef CONFIG_SYS_I2C
  64#define CONFIG_SYS_I2C_FSL
  65#define CONFIG_SYS_FSL_I2C_SPEED        400000
  66#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  67#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
  68#define CONFIG_SYS_FSL_I2C2_SPEED       400000
  69#define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
  70#define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
  71
  72#define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
  73#define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
  74
  75#define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
  76#define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
  77#define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
  78#define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
  79#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
  80#define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
  81#define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
  82
  83/* Don't probe these addresses: */
  84#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
  85                                 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
  86                                 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
  87                                 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
  88/* Bit definitions for the 8574[A] I2C expander */
  89                                /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
  90#define I2C_8574_REVISION       0x03
  91#define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
  92#define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
  93#define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
  94#define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
  95
  96#endif
  97
  98/* Compact Flash */
  99#ifdef CONFIG_COMPACT_FLASH
 100
 101#define CONFIG_SYS_IDE_MAXBUS           1
 102#define CONFIG_SYS_IDE_MAXDEVICE        1
 103
 104#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 105#define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
 106#define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
 107#define CONFIG_SYS_ATA_REG_OFFSET       0
 108#define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
 109#define CONFIG_SYS_ATA_STRIDE           2
 110
 111/* If a CF card is not inserted, time out quickly */
 112#define ATA_RESET_TIME  1
 113
 114#endif
 115
 116/*
 117 * SATA
 118 */
 119#ifdef CONFIG_SATA_SIL3114
 120
 121#define CONFIG_SYS_SATA_MAX_DEVICE      4
 122#define CONFIG_LBA48
 123
 124#endif
 125
 126#ifdef CONFIG_SYS_USB_HOST
 127/*
 128 * Support USB
 129 */
 130#define CONFIG_USB_EHCI_FSL
 131
 132/* Current USB implementation supports the only USB controller,
 133 * so we have to choose between the MPH or the DR ones */
 134#if 1
 135#define CONFIG_HAS_FSL_MPH_USB
 136#else
 137#define CONFIG_HAS_FSL_DR_USB
 138#endif
 139
 140#endif
 141
 142/*
 143 * DDR Setup
 144 */
 145#define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory*/
 146#define CONFIG_SYS_83XX_DDR_USES_CS0
 147#define CONFIG_SYS_MEMTEST_START        0x1000  /* memtest region */
 148#define CONFIG_SYS_MEMTEST_END          0x2000
 149
 150#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 151                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 152
 153#define CONFIG_VERY_BIG_RAM
 154#define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 155
 156#ifdef CONFIG_SYS_I2C
 157#define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
 158#endif
 159
 160/* No SPD? Then manually set up DDR parameters */
 161#ifndef CONFIG_SPD_EEPROM
 162    #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
 163    #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
 164                                        | CSCONFIG_ROW_BIT_13 \
 165                                        | CSCONFIG_COL_BIT_10)
 166
 167    #define CONFIG_SYS_DDR_TIMING_1     0x26242321
 168    #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
 169#endif
 170
 171/*
 172 *Flash on the Local Bus
 173 */
 174
 175#define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 176#define CONFIG_SYS_FLASH_EMPTY_INFO
 177/* 127 64KB sectors + 8 8KB sectors per device */
 178#define CONFIG_SYS_MAX_FLASH_SECT       135
 179#define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 180#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 181#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 182
 183/* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 184boards, we say we have two, but don't display a message if we find only one. */
 185#define CONFIG_SYS_FLASH_QUIET_TEST
 186#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 187#define CONFIG_SYS_FLASH_BANKS_LIST     \
 188                {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 189#define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
 190
 191/* Vitesse 7385 */
 192
 193#ifdef CONFIG_VSC7385_ENET
 194
 195#define CONFIG_TSEC2
 196
 197/* The flash address and size of the VSC7385 firmware image */
 198#define CONFIG_VSC7385_IMAGE            0xFEFFE000
 199#define CONFIG_VSC7385_IMAGE_SIZE       8192
 200
 201#endif
 202
 203/*
 204 * BRx, ORx, LBLAWBARx, and LBLAWARx
 205 */
 206
 207
 208/* Vitesse 7385 */
 209
 210#define CONFIG_SYS_VSC7385_BASE 0xF8000000
 211
 212#define CONFIG_SYS_LED_BASE     0xF9000000
 213
 214
 215/* Compact Flash */
 216
 217#ifdef CONFIG_COMPACT_FLASH
 218
 219#define CONFIG_SYS_CF_BASE      0xF0000000
 220
 221
 222#endif
 223
 224/*
 225 * U-Boot memory configuration
 226 */
 227#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 228
 229#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 230#define CONFIG_SYS_RAMBOOT
 231#else
 232#undef  CONFIG_SYS_RAMBOOT
 233#endif
 234
 235#define CONFIG_SYS_INIT_RAM_LOCK
 236#define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 237#define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 238
 239#define CONFIG_SYS_GBL_DATA_OFFSET      \
 240                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 241#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 242
 243/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 244#define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 245#define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 246
 247/*
 248 * Serial Port
 249 */
 250#define CONFIG_SYS_NS16550_SERIAL
 251#define CONFIG_SYS_NS16550_REG_SIZE     1
 252#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 253
 254#define CONFIG_SYS_BAUDRATE_TABLE  \
 255                {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 256
 257#define CONSOLE                 ttyS0
 258
 259#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 260#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 261
 262/*
 263 * PCI
 264 */
 265#ifdef CONFIG_PCI
 266#define CONFIG_PCI_INDIRECT_BRIDGE
 267
 268#define CONFIG_MPC83XX_PCI2
 269
 270/*
 271 * General PCI
 272 * Addresses are mapped 1-1.
 273 */
 274#define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 275#define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 276#define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 277#define CONFIG_SYS_PCI1_MMIO_BASE       \
 278                        (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 279#define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 280#define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 281#define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 282#define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 283#define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
 284
 285#ifdef CONFIG_MPC83XX_PCI2
 286#define CONFIG_SYS_PCI2_MEM_BASE        \
 287                        (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 288#define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 289#define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 290#define CONFIG_SYS_PCI2_MMIO_BASE       \
 291                        (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 292#define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 293#define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 294#define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 295#define CONFIG_SYS_PCI2_IO_PHYS         \
 296                        (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 297#define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
 298#endif
 299
 300#ifndef CONFIG_PCI_PNP
 301    #define PCI_ENET0_IOADDR    0x00000000
 302    #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
 303    #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
 304#endif
 305
 306#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 307
 308#endif
 309
 310/* TSEC */
 311
 312#ifdef CONFIG_TSEC_ENET
 313#define CONFIG_TSEC1
 314
 315#ifdef CONFIG_TSEC1
 316#define CONFIG_HAS_ETH0
 317#define CONFIG_TSEC1_NAME  "TSEC0"
 318#define CONFIG_SYS_TSEC1_OFFSET 0x24000
 319#define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
 320#define TSEC1_PHYIDX            0
 321#define TSEC1_FLAGS             TSEC_GIGABIT
 322#endif
 323
 324#ifdef CONFIG_TSEC2
 325#define CONFIG_HAS_ETH1
 326#define CONFIG_TSEC2_NAME  "TSEC1"
 327#define CONFIG_SYS_TSEC2_OFFSET 0x25000
 328
 329#define TSEC2_PHY_ADDR          4
 330#define TSEC2_PHYIDX            0
 331#define TSEC2_FLAGS             TSEC_GIGABIT
 332#endif
 333
 334#define CONFIG_ETHPRIME         "Freescale TSEC"
 335
 336#endif
 337
 338/*
 339 * Environment
 340 */
 341#define CONFIG_ENV_OVERWRITE
 342
 343#define CONFIG_LOADS_ECHO       /* echo on for serial download */
 344#define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 345
 346/*
 347 * BOOTP options
 348 */
 349#define CONFIG_BOOTP_BOOTFILESIZE
 350
 351/* Watchdog */
 352#undef CONFIG_WATCHDOG          /* watchdog disabled */
 353
 354/*
 355 * Miscellaneous configurable options
 356 */
 357
 358#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 359#define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 360
 361/*
 362 * For booting Linux, the board info and command line data
 363 * have to be in the first 256 MB of memory, since this is
 364 * the maximum mapped by the Linux kernel during initialization.
 365 */
 366                                /* Initial Memory map for Linux*/
 367#define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 368#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 369
 370/*
 371 * System performance
 372 */
 373#define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 374#define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 375#define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
 376#define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
 377
 378/*
 379 * System IO Config
 380 */
 381/* Needed for gigabit to work on TSEC 1 */
 382#define CONFIG_SYS_SICRH SICRH_TSOBI1
 383                                /* USB DR as device + USB MPH as host */
 384#define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
 385
 386#if defined(CONFIG_CMD_KGDB)
 387#define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 388#endif
 389
 390/*
 391 * Environment Configuration
 392 */
 393#define CONFIG_ENV_OVERWRITE
 394
 395#define CONFIG_NETDEV           "eth0"
 396
 397/* Default path and filenames */
 398#define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 399#define CONFIG_BOOTFILE         "uImage"
 400                                /* U-Boot image on TFTP server */
 401#define CONFIG_UBOOTPATH        "u-boot.bin"
 402
 403#ifdef CONFIG_TARGET_MPC8349ITX
 404#define CONFIG_FDTFILE          "mpc8349emitx.dtb"
 405#else
 406#define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
 407#endif
 408
 409
 410#define CONFIG_EXTRA_ENV_SETTINGS \
 411        "console=" __stringify(CONSOLE) "\0"                    \
 412        "netdev=" CONFIG_NETDEV "\0"                                    \
 413        "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 414        "tftpflash=tftpboot $loadaddr $uboot; "                         \
 415                "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 416                        " +$filesize; " \
 417                "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 418                        " +$filesize; " \
 419                "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 420                        " $filesize; "  \
 421                "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 422                        " +$filesize; " \
 423                "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 424                        " $filesize\0"  \
 425        "fdtaddr=780000\0"                                              \
 426        "fdtfile=" CONFIG_FDTFILE "\0"
 427
 428#define CONFIG_NFSBOOTCOMMAND                                           \
 429        "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
 430        " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 431        " console=$console,$baudrate $othbootargs; "                    \
 432        "tftp $loadaddr $bootfile;"                                     \
 433        "tftp $fdtaddr $fdtfile;"                                       \
 434        "bootm $loadaddr - $fdtaddr"
 435
 436#define CONFIG_RAMBOOTCOMMAND                                           \
 437        "setenv bootargs root=/dev/ram rw"                              \
 438        " console=$console,$baudrate $othbootargs; "                    \
 439        "tftp $ramdiskaddr $ramdiskfile;"                               \
 440        "tftp $loadaddr $bootfile;"                                     \
 441        "tftp $fdtaddr $fdtfile;"                                       \
 442        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 443
 444#endif
 445