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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13
14
15
16
17#ifndef CONFIG_DIRECT_NOR_BOOT
18#define CONFIG_USE_SPIFLASH
19#endif
20
21
22
23
24#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
25#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
26#define CONFIG_SYS_OSCIN_FREQ 24000000
27#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
28#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
29#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
30
31#ifdef CONFIG_DIRECT_NOR_BOOT
32#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
33#endif
34
35
36
37
38#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024)
39#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE
40#define PHYS_SDRAM_1_SIZE (64 << 20)
41#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20)
42#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
43#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
44
45#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
46
47
48#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
49
50#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
51 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
52 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
53 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
54 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
55 DAVINCI_SYSCFG_SUSPSRC_I2C)
56
57
58
59
60
61#define CONFIG_SYS_DA850_PLL0_PLLM 24
62#define CONFIG_SYS_DA850_PLL1_PLLM 21
63
64
65
66
67#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
68 DV_DDR_PHY_EXT_STRBEN | \
69 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
70
71#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
72 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
73 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
74 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
75 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
76 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
77 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
78 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
79
80
81#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
82
83#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
84 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
85 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
86 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
87 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
88 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
89 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
90 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
91 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
92
93#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
94 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
95 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
96 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
97 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
98 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
99 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
100 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
101
102#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
103#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
104
105
106
107
108#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
109
110#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
111
112#ifdef CONFIG_USE_SPIFLASH
113#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
114#endif
115
116
117
118
119#ifndef CONFIG_SPL_BUILD
120#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
121#endif
122
123
124
125
126#ifdef CONFIG_MTD_RAW_NAND
127#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
128#define CONFIG_SYS_NAND_PAGE_2K
129#define CONFIG_SYS_NAND_CS 3
130#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
131#define CONFIG_SYS_NAND_MASK_CLE 0x10
132#define CONFIG_SYS_NAND_MASK_ALE 0x8
133#undef CONFIG_SYS_NAND_HW_ECC
134#define CONFIG_SYS_MAX_NAND_DEVICE 1
135#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
136#define CONFIG_SYS_NAND_5_ADDR_CYCLE
137#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
138#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
139#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
140#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
141#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
142#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
143 CONFIG_SYS_NAND_U_BOOT_SIZE - \
144 CONFIG_SYS_MALLOC_LEN - \
145 GENERATED_GBL_DATA_SIZE)
146#define CONFIG_SYS_NAND_ECCPOS { \
147 24, 25, 26, 27, 28, \
148 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
149 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
150 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
151 59, 60, 61, 62, 63 }
152#define CONFIG_SYS_NAND_PAGE_COUNT 64
153#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
154#define CONFIG_SYS_NAND_ECCSIZE 512
155#define CONFIG_SYS_NAND_ECCBYTES 10
156#define CONFIG_SYS_NAND_OOBSIZE 64
157#define CONFIG_SPL_NAND_BASE
158#define CONFIG_SPL_NAND_DRIVERS
159#define CONFIG_SPL_NAND_ECC
160#define CONFIG_SPL_NAND_LOAD
161
162#ifndef CONFIG_SPL_BUILD
163#define CONFIG_SYS_NAND_SELF_INIT
164#endif
165#endif
166
167
168
169
170#ifdef CONFIG_DRIVER_TI_EMAC
171#define CONFIG_BOOTP_DNS2
172#define CONFIG_BOOTP_SEND_HOSTNAME
173#define CONFIG_NET_RETRY_COUNT 10
174#endif
175
176#ifdef CONFIG_USE_NOR
177#define CONFIG_SYS_MAX_FLASH_BANKS 1
178#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10)
179#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
180#define PHYS_FLASH_SIZE (8 << 20)
181#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
182 + 3)
183#endif
184
185
186
187
188#define CONFIG_BOOTFILE "uImage"
189#define CONFIG_SYS_CBSIZE 1024
190#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
191#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
192
193
194
195
196#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
197#define CONFIG_HWCONFIG
198#define CONFIG_CMDLINE_TAG
199#define CONFIG_REVISION_TAG
200#define CONFIG_SETUP_MEMORY_TAGS
201
202#define CONFIG_BOOTCOMMAND \
203 "run envboot; " \
204 "run mmcboot; "
205
206#define DEFAULT_LINUX_BOOT_ENV \
207 "loadaddr=0xc0700000\0" \
208 "fdtaddr=0xc0600000\0" \
209 "scriptaddr=0xc0600000\0"
210
211#include <environment/ti/mmc.h>
212
213#define CONFIG_EXTRA_ENV_SETTINGS \
214 DEFAULT_LINUX_BOOT_ENV \
215 DEFAULT_MMC_TI_ARGS \
216 "bootpart=0:2\0" \
217 "bootdir=/boot\0" \
218 "bootfile=zImage\0" \
219 "fdtfile=da850-evm.dtb\0" \
220 "boot_fdt=yes\0" \
221 "boot_fit=0\0" \
222 "console=ttyS2,115200n8\0" \
223 "hwconfig=dsp:wake=yes"
224
225#ifdef CONFIG_CMD_BDI
226#define CONFIG_CLOCKS
227#endif
228
229#if !defined(CONFIG_MTD_RAW_NAND) && \
230 !defined(CONFIG_USE_NOR) && \
231 !defined(CONFIG_USE_SPIFLASH)
232#endif
233
234
235#define CONFIG_USB_OHCI_NEW
236#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
237
238#ifndef CONFIG_DIRECT_NOR_BOOT
239
240#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
241 CONFIG_SYS_MALLOC_LEN)
242#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
243#define CONFIG_SPL_STACK 0x8001ff00
244#define CONFIG_SPL_MAX_FOOTPRINT 32768
245#define CONFIG_SPL_PAD_TO 32768
246#endif
247
248
249
250
251#define CONFIG_SYS_SDRAM_BASE 0xc0000000
252
253#ifdef CONFIG_DIRECT_NOR_BOOT
254#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
255#else
256#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
257 GENERATED_GBL_DATA_SIZE)
258#endif
259
260#include <asm/arch/hardware.h>
261
262#endif
263