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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <asm/hardware.h>
13
14
15
16
17#define CONFIG_SKIP_LOWLEVEL_INIT
18
19
20#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
21
22
23
24
25#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
26#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
27
28
29#define CONFIG_SRAM_BASE 0x00300000
30#define CONFIG_SRAM_SIZE (32 << 10)
31#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
32 GENERATED_GBL_DATA_SIZE)
33
34
35#define CONFIG_SYS_SDRAM_BASE 0x20000000
36#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
37#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
38#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
39#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
40#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
41#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
42 - CONFIG_SYS_MALLOC_LEN)
43
44
45# define CONFIG_SYS_MAX_FLASH_BANKS 1
46# define CONFIG_SYS_FLASH_BASE 0x00200000
47# define CONFIG_AT91_EFLASH
48# define CONFIG_SYS_MAX_FLASH_SECT 32
49# define CONFIG_EFLASH_PROTSECTORS 1
50
51
52
53
54
55#ifdef CONFIG_CMD_NAND
56#define CONFIG_SYS_MAX_NAND_DEVICE 1
57#define CONFIG_SYS_NAND_BASE 0x40000000
58#define CONFIG_SYS_NAND_DBW_8
59
60#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
61
62#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
63#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
64#endif
65
66
67#ifdef CONFIG_CMD_JFFS2
68#define CONFIG_JFFS2_CMDLINE
69#define CONFIG_JFFS2_NAND
70#endif
71
72
73#define CONFIG_NET_RETRY_COUNT 20
74#define CONFIG_MACB
75#define CONFIG_RMII
76#define CONFIG_PHY_ID 0
77#define CONFIG_MACB_SEARCH_PHY
78
79
80#ifdef CONFIG_CMD_MMC
81#define CONFIG_GENERIC_ATMEL_MCI
82#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
83#endif
84
85
86#ifdef CONFIG_CMD_USB
87#define CONFIG_USB_ATMEL
88#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
89#define CONFIG_USB_OHCI_NEW
90#define CONFIG_SYS_USB_OHCI_CPU_INIT
91#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
92#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
93#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
94#endif
95
96
97#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
98#define CONFIG_RTC_PCF8563
99#define CONFIG_SYS_I2C_RTC_ADDR 0x51
100#endif
101
102
103#define CONFIG_SYS_MAX_I2C_BUS 1
104
105#define CONFIG_SYS_I2C
106#define CONFIG_SYS_I2C_SOFT
107#define CONFIG_SYS_I2C_SOFT_SPEED 100000
108#define CONFIG_SYS_I2C_SOFT_SLAVE 0
109
110#define I2C_SOFT_DECLARATIONS
111
112#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
113#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
114
115#define I2C_INIT { \
116 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
117 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
118 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
119 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
120 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
121}
122
123#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
124#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
125#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
126#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
127#define I2C_DELAY udelay(100)
128#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
129
130
131#ifdef CONFIG_CMD_DHCP
132#define CONFIG_BOOTP_BOOTFILESIZE
133#define CONFIG_SYS_AUTOLOAD "n"
134#endif
135
136
137
138
139#define CONFIG_CMDLINE_TAG
140#define CONFIG_SETUP_MEMORY_TAGS
141#define CONFIG_INITRD_TAG
142#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
143 "sf read 0x22000000 0xc6000 0x294000; " \
144 "bootm 0x22000000"
145
146
147
148#endif
149