1
2
3
4#define BOOTFLASH_START 0xF0000000
5
6
7
8
9#define CONFIG_SYS_SDRAM_BASE 0x00000000
10#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000)
11
12#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
13 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
14
15#define CFG_83XX_DDR_USES_CS0
16
17
18
19
20#define CONFIG_DDR_II
21#define CONFIG_SYS_DDR_SIZE 2048
22
23
24
25
26#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
27#define CONFIG_SYS_FLASH_BASE 0xF0000000
28
29#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
30#define CONFIG_SYS_RAMBOOT
31#endif
32
33
34#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
35
36
37
38
39#define CONFIG_SYS_INIT_RAM_LOCK
40#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
41#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
42#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
43 GENERATED_GBL_DATA_SIZE)
44
45
46
47
48
49
50
51
52
53
54
55
56
57#define CONFIG_SYS_FLASH_SIZE 256
58
59#define CONFIG_SYS_MAX_FLASH_BANKS 1
60#define CONFIG_SYS_MAX_FLASH_SECT 512
61#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
62
63
64
65
66#define CONFIG_SYS_NS16550_SERIAL
67#define CONFIG_SYS_NS16550_REG_SIZE 1
68#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
69
70#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
71#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
72
73
74#define CONFIG_SYS_I2C
75#define CONFIG_SYS_NUM_I2C_BUSES 4
76#define CONFIG_SYS_I2C_MAX_HOPS 1
77#define CONFIG_SYS_I2C_FSL
78#define CONFIG_SYS_FSL_I2C_SPEED 200000
79#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
80#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
81#define CONFIG_SYS_I2C_OFFSET 0x3000
82#define CONFIG_SYS_FSL_I2C2_SPEED 200000
83#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
84#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
85#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
86 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
87 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
88 {1, {I2C_NULL_HOP} } }
89
90#if defined(CONFIG_CMD_NAND)
91#define CONFIG_NAND_KMETER1
92#define CONFIG_SYS_MAX_NAND_DEVICE 1
93#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
94#endif
95
96
97
98
99
100
101#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
102
103
104
105
106
107#ifndef CONFIG_SYS_RAMBOOT
108
109#endif
110
111
112
113
114#define CONFIG_ENV_OVERWRITE
115#ifndef CONFIG_KM_DEF_ENV
116#define CONFIG_KM_DEF_ENV "km-common=empty\0"
117#endif
118
119#ifndef CONFIG_KM_DEF_ARCH
120#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
121#endif
122
123#define CONFIG_EXTRA_ENV_SETTINGS \
124 CONFIG_KM_DEF_ENV \
125 CONFIG_KM_DEF_ARCH \
126 "newenv=" \
127 "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \
128 "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \
129 "unlock=yes\0" \
130 ""
131
132#if defined(CONFIG_UEC_ETH)
133#define CONFIG_HAS_ETH0
134#endif
135
136
137
138
139#define CONFIG_UEC_ETH
140#define CONFIG_ETHPRIME "UEC0"
141