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10#ifndef _PCI_H
11#define _PCI_H
12
13#define PCI_CFG_SPACE_SIZE 256
14#define PCI_CFG_SPACE_EXP_SIZE 4096
15
16
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18
19
20#define PCI_STD_HEADER_SIZEOF 64
21#define PCI_VENDOR_ID 0x00
22#define PCI_DEVICE_ID 0x02
23#define PCI_COMMAND 0x04
24#define PCI_COMMAND_IO 0x1
25#define PCI_COMMAND_MEMORY 0x2
26#define PCI_COMMAND_MASTER 0x4
27#define PCI_COMMAND_SPECIAL 0x8
28#define PCI_COMMAND_INVALIDATE 0x10
29#define PCI_COMMAND_VGA_PALETTE 0x20
30#define PCI_COMMAND_PARITY 0x40
31#define PCI_COMMAND_WAIT 0x80
32#define PCI_COMMAND_SERR 0x100
33#define PCI_COMMAND_FAST_BACK 0x200
34
35#define PCI_STATUS 0x06
36#define PCI_STATUS_CAP_LIST 0x10
37#define PCI_STATUS_66MHZ 0x20
38#define PCI_STATUS_UDF 0x40
39#define PCI_STATUS_FAST_BACK 0x80
40#define PCI_STATUS_PARITY 0x100
41#define PCI_STATUS_DEVSEL_MASK 0x600
42#define PCI_STATUS_DEVSEL_FAST 0x000
43#define PCI_STATUS_DEVSEL_MEDIUM 0x200
44#define PCI_STATUS_DEVSEL_SLOW 0x400
45#define PCI_STATUS_SIG_TARGET_ABORT 0x800
46#define PCI_STATUS_REC_TARGET_ABORT 0x1000
47#define PCI_STATUS_REC_MASTER_ABORT 0x2000
48#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000
49#define PCI_STATUS_DETECTED_PARITY 0x8000
50
51#define PCI_CLASS_REVISION 0x08
52
53#define PCI_REVISION_ID 0x08
54#define PCI_CLASS_PROG 0x09
55#define PCI_CLASS_DEVICE 0x0a
56#define PCI_CLASS_CODE 0x0b
57#define PCI_CLASS_CODE_TOO_OLD 0x00
58#define PCI_CLASS_CODE_STORAGE 0x01
59#define PCI_CLASS_CODE_NETWORK 0x02
60#define PCI_CLASS_CODE_DISPLAY 0x03
61#define PCI_CLASS_CODE_MULTIMEDIA 0x04
62#define PCI_CLASS_CODE_MEMORY 0x05
63#define PCI_CLASS_CODE_BRIDGE 0x06
64#define PCI_CLASS_CODE_COMM 0x07
65#define PCI_CLASS_CODE_PERIPHERAL 0x08
66#define PCI_CLASS_CODE_INPUT 0x09
67#define PCI_CLASS_CODE_DOCKING 0x0A
68#define PCI_CLASS_CODE_PROCESSOR 0x0B
69#define PCI_CLASS_CODE_SERIAL 0x0C
70#define PCI_CLASS_CODE_WIRELESS 0x0D
71#define PCI_CLASS_CODE_I2O 0x0E
72#define PCI_CLASS_CODE_SATELLITE 0x0F
73#define PCI_CLASS_CODE_CRYPTO 0x10
74#define PCI_CLASS_CODE_DATA 0x11
75
76#define PCI_CLASS_CODE_OTHER 0xFF
77
78#define PCI_CLASS_SUB_CODE 0x0a
79#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
80#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
81#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
82#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
83#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
84#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
85#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
86#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
87#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
88#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
89#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
90#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
91#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
92#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
93#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
94#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
95#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
96#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
97#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
98#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
99#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
100#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
101#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
102#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
103#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
104#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
105#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
106#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
107#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
108#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
109#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
110#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
111#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
112#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
113#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
114#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
115#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
116#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
117#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
118#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
119#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
120#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
121#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
122#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
123#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
124#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
125#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
126#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
127#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
128#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
129#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
130#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
131#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
132#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
133#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
134#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
135#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
136#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
137#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
138#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
139#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
140#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
141#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
142#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
143#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
144#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
145#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
146#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
147#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
148#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
149#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
150#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
151#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
152#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
153#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
154#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
155#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
156#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
157#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
158#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
159#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
160#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
161#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
162#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
163#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
164#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
165#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
166#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
167#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
168#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
169#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
170#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
171#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
172#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
173#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
174#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
175#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
176#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
177#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
178#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
179#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
180#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
181
182#define PCI_CACHE_LINE_SIZE 0x0c
183#define PCI_LATENCY_TIMER 0x0d
184#define PCI_HEADER_TYPE 0x0e
185#define PCI_HEADER_TYPE_NORMAL 0
186#define PCI_HEADER_TYPE_BRIDGE 1
187#define PCI_HEADER_TYPE_CARDBUS 2
188
189#define PCI_BIST 0x0f
190#define PCI_BIST_CODE_MASK 0x0f
191#define PCI_BIST_START 0x40
192#define PCI_BIST_CAPABLE 0x80
193
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198
199
200#define PCI_BASE_ADDRESS_0 0x10
201#define PCI_BASE_ADDRESS_1 0x14
202#define PCI_BASE_ADDRESS_2 0x18
203#define PCI_BASE_ADDRESS_3 0x1c
204#define PCI_BASE_ADDRESS_4 0x20
205#define PCI_BASE_ADDRESS_5 0x24
206#define PCI_BASE_ADDRESS_SPACE 0x01
207#define PCI_BASE_ADDRESS_SPACE_IO 0x01
208#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
209#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
210#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00
211#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02
212#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04
213#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08
214#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
215#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
216
217
218
219#define pci_offset_to_barnum(offset) \
220 (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
221
222
223#define PCI_CARDBUS_CIS 0x28
224#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
225#define PCI_SUBSYSTEM_ID 0x2e
226#define PCI_ROM_ADDRESS 0x30
227#define PCI_ROM_ADDRESS_ENABLE 0x01
228#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
229
230#define PCI_CAPABILITY_LIST 0x34
231
232
233#define PCI_INTERRUPT_LINE 0x3c
234#define PCI_INTERRUPT_PIN 0x3d
235#define PCI_MIN_GNT 0x3e
236#define PCI_MAX_LAT 0x3f
237
238#define PCI_INTERRUPT_LINE_DISABLE 0xff
239
240
241#define PCI_PRIMARY_BUS 0x18
242#define PCI_SECONDARY_BUS 0x19
243#define PCI_SUBORDINATE_BUS 0x1a
244#define PCI_SEC_LATENCY_TIMER 0x1b
245#define PCI_IO_BASE 0x1c
246#define PCI_IO_LIMIT 0x1d
247#define PCI_IO_RANGE_TYPE_MASK 0x0f
248#define PCI_IO_RANGE_TYPE_16 0x00
249#define PCI_IO_RANGE_TYPE_32 0x01
250#define PCI_IO_RANGE_MASK ~0x0f
251#define PCI_SEC_STATUS 0x1e
252#define PCI_MEMORY_BASE 0x20
253#define PCI_MEMORY_LIMIT 0x22
254#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
255#define PCI_MEMORY_RANGE_MASK ~0x0f
256#define PCI_PREF_MEMORY_BASE 0x24
257#define PCI_PREF_MEMORY_LIMIT 0x26
258#define PCI_PREF_RANGE_TYPE_MASK 0x0f
259#define PCI_PREF_RANGE_TYPE_32 0x00
260#define PCI_PREF_RANGE_TYPE_64 0x01
261#define PCI_PREF_RANGE_MASK ~0x0f
262#define PCI_PREF_BASE_UPPER32 0x28
263#define PCI_PREF_LIMIT_UPPER32 0x2c
264#define PCI_IO_BASE_UPPER16 0x30
265#define PCI_IO_LIMIT_UPPER16 0x32
266
267
268#define PCI_ROM_ADDRESS1 0x38
269
270#define PCI_BRIDGE_CONTROL 0x3e
271#define PCI_BRIDGE_CTL_PARITY 0x01
272#define PCI_BRIDGE_CTL_SERR 0x02
273#define PCI_BRIDGE_CTL_NO_ISA 0x04
274#define PCI_BRIDGE_CTL_VGA 0x08
275#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20
276#define PCI_BRIDGE_CTL_BUS_RESET 0x40
277#define PCI_BRIDGE_CTL_FAST_BACK 0x80
278
279
280#define PCI_CB_CAPABILITY_LIST 0x14
281
282#define PCI_CB_SEC_STATUS 0x16
283#define PCI_CB_PRIMARY_BUS 0x18
284#define PCI_CB_CARD_BUS 0x19
285#define PCI_CB_SUBORDINATE_BUS 0x1a
286#define PCI_CB_LATENCY_TIMER 0x1b
287#define PCI_CB_MEMORY_BASE_0 0x1c
288#define PCI_CB_MEMORY_LIMIT_0 0x20
289#define PCI_CB_MEMORY_BASE_1 0x24
290#define PCI_CB_MEMORY_LIMIT_1 0x28
291#define PCI_CB_IO_BASE_0 0x2c
292#define PCI_CB_IO_BASE_0_HI 0x2e
293#define PCI_CB_IO_LIMIT_0 0x30
294#define PCI_CB_IO_LIMIT_0_HI 0x32
295#define PCI_CB_IO_BASE_1 0x34
296#define PCI_CB_IO_BASE_1_HI 0x36
297#define PCI_CB_IO_LIMIT_1 0x38
298#define PCI_CB_IO_LIMIT_1_HI 0x3a
299#define PCI_CB_IO_RANGE_MASK ~0x03
300
301#define PCI_CB_BRIDGE_CONTROL 0x3e
302#define PCI_CB_BRIDGE_CTL_PARITY 0x01
303#define PCI_CB_BRIDGE_CTL_SERR 0x02
304#define PCI_CB_BRIDGE_CTL_ISA 0x04
305#define PCI_CB_BRIDGE_CTL_VGA 0x08
306#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
307#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40
308#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80
309#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
310#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
311#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
312#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
313#define PCI_CB_SUBSYSTEM_ID 0x42
314#define PCI_CB_LEGACY_MODE_BASE 0x44
315
316
317
318
319#define PCI_CAP_LIST_ID 0
320#define PCI_CAP_ID_PM 0x01
321#define PCI_CAP_ID_AGP 0x02
322#define PCI_CAP_ID_VPD 0x03
323#define PCI_CAP_ID_SLOTID 0x04
324#define PCI_CAP_ID_MSI 0x05
325#define PCI_CAP_ID_CHSWP 0x06
326#define PCI_CAP_ID_PCIX 0x07
327#define PCI_CAP_ID_HT 0x08
328#define PCI_CAP_ID_VNDR 0x09
329#define PCI_CAP_ID_DBG 0x0A
330#define PCI_CAP_ID_CCRC 0x0B
331#define PCI_CAP_ID_SHPC 0x0C
332#define PCI_CAP_ID_SSVID 0x0D
333#define PCI_CAP_ID_AGP3 0x0E
334#define PCI_CAP_ID_SECDEV 0x0F
335#define PCI_CAP_ID_EXP 0x10
336#define PCI_CAP_ID_MSIX 0x11
337#define PCI_CAP_ID_SATA 0x12
338#define PCI_CAP_ID_AF 0x13
339#define PCI_CAP_ID_EA 0x14
340#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
341#define PCI_CAP_LIST_NEXT 1
342#define PCI_CAP_FLAGS 2
343#define PCI_CAP_SIZEOF 4
344
345
346
347#define PCI_PM_CAP_VER_MASK 0x0007
348#define PCI_PM_CAP_PME_CLOCK 0x0008
349#define PCI_PM_CAP_AUX_POWER 0x0010
350#define PCI_PM_CAP_DSI 0x0020
351#define PCI_PM_CAP_D1 0x0200
352#define PCI_PM_CAP_D2 0x0400
353#define PCI_PM_CAP_PME 0x0800
354#define PCI_PM_CTRL 4
355#define PCI_PM_CTRL_STATE_MASK 0x0003
356#define PCI_PM_CTRL_PME_ENABLE 0x0100
357#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00
358#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000
359#define PCI_PM_CTRL_PME_STATUS 0x8000
360#define PCI_PM_PPB_EXTENSIONS 6
361#define PCI_PM_PPB_B2_B3 0x40
362#define PCI_PM_BPCC_ENABLE 0x80
363#define PCI_PM_DATA_REGISTER 7
364#define PCI_PM_SIZEOF 8
365
366
367
368#define PCI_AGP_VERSION 2
369#define PCI_AGP_RFU 3
370#define PCI_AGP_STATUS 4
371#define PCI_AGP_STATUS_RQ_MASK 0xff000000
372#define PCI_AGP_STATUS_SBA 0x0200
373#define PCI_AGP_STATUS_64BIT 0x0020
374#define PCI_AGP_STATUS_FW 0x0010
375#define PCI_AGP_STATUS_RATE4 0x0004
376#define PCI_AGP_STATUS_RATE2 0x0002
377#define PCI_AGP_STATUS_RATE1 0x0001
378#define PCI_AGP_COMMAND 8
379#define PCI_AGP_COMMAND_RQ_MASK 0xff000000
380#define PCI_AGP_COMMAND_SBA 0x0200
381#define PCI_AGP_COMMAND_AGP 0x0100
382#define PCI_AGP_COMMAND_64BIT 0x0020
383#define PCI_AGP_COMMAND_FW 0x0010
384#define PCI_AGP_COMMAND_RATE4 0x0004
385#define PCI_AGP_COMMAND_RATE2 0x0002
386#define PCI_AGP_COMMAND_RATE1 0x0001
387#define PCI_AGP_SIZEOF 12
388
389
390
391#define PCI_X_CMD_DPERR_E 0x0001
392#define PCI_X_CMD_ERO 0x0002
393#define PCI_X_CMD_MAX_READ 0x0000
394#define PCI_X_CMD_MAX_SPLIT 0x0030
395#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3)
396
397
398
399
400#define PCI_SID_ESR 2
401#define PCI_SID_ESR_NSLOTS 0x1f
402#define PCI_SID_ESR_FIC 0x20
403#define PCI_SID_CHASSIS_NR 3
404
405
406
407#define PCI_MSI_FLAGS 2
408#define PCI_MSI_FLAGS_64BIT 0x80
409#define PCI_MSI_FLAGS_QSIZE 0x70
410#define PCI_MSI_FLAGS_QMASK 0x0e
411#define PCI_MSI_FLAGS_ENABLE 0x01
412#define PCI_MSI_FLAGS_MASKBIT 0x0100
413#define PCI_MSI_RFU 3
414#define PCI_MSI_ADDRESS_LO 4
415#define PCI_MSI_ADDRESS_HI 8
416#define PCI_MSI_DATA_32 8
417#define PCI_MSI_DATA_64 12
418
419#define PCI_MAX_PCI_DEVICES 32
420#define PCI_MAX_PCI_FUNCTIONS 8
421
422#define PCI_FIND_CAP_TTL 0x48
423#define CAP_START_POS 0x40
424
425
426#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
427#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
428#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
429
430#define PCI_EXT_CAP_ID_ERR 0x01
431#define PCI_EXT_CAP_ID_VC 0x02
432#define PCI_EXT_CAP_ID_DSN 0x03
433#define PCI_EXT_CAP_ID_PWR 0x04
434#define PCI_EXT_CAP_ID_RCLD 0x05
435#define PCI_EXT_CAP_ID_RCILC 0x06
436#define PCI_EXT_CAP_ID_RCEC 0x07
437#define PCI_EXT_CAP_ID_MFVC 0x08
438#define PCI_EXT_CAP_ID_VC9 0x09
439#define PCI_EXT_CAP_ID_RCRB 0x0A
440#define PCI_EXT_CAP_ID_VNDR 0x0B
441#define PCI_EXT_CAP_ID_CAC 0x0C
442#define PCI_EXT_CAP_ID_ACS 0x0D
443#define PCI_EXT_CAP_ID_ARI 0x0E
444#define PCI_EXT_CAP_ID_ATS 0x0F
445#define PCI_EXT_CAP_ID_SRIOV 0x10
446#define PCI_EXT_CAP_ID_MRIOV 0x11
447#define PCI_EXT_CAP_ID_MCAST 0x12
448#define PCI_EXT_CAP_ID_PRI 0x13
449#define PCI_EXT_CAP_ID_AMD_XXX 0x14
450#define PCI_EXT_CAP_ID_REBAR 0x15
451#define PCI_EXT_CAP_ID_DPA 0x16
452#define PCI_EXT_CAP_ID_TPH 0x17
453#define PCI_EXT_CAP_ID_LTR 0x18
454#define PCI_EXT_CAP_ID_SECPCI 0x19
455#define PCI_EXT_CAP_ID_PMUX 0x1A
456#define PCI_EXT_CAP_ID_PASID 0x1B
457#define PCI_EXT_CAP_ID_DPC 0x1D
458#define PCI_EXT_CAP_ID_L1SS 0x1E
459#define PCI_EXT_CAP_ID_PTM 0x1F
460#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
461
462
463#define PCI_EA_NUM_ENT 2
464#define PCI_EA_NUM_ENT_MASK 0x3f
465#define PCI_EA_FIRST_ENT 4
466#define PCI_EA_ES 0x00000007
467#define PCI_EA_BEI 0x000000f0
468
469
470#define PCI_EA_IS_64 0x00000002
471#define PCI_EA_FIELD_MASK 0xfffffffc
472
473
474#define PCI_EXP_DEVCAP 4
475#define PCI_EXP_DEVCAP_FLR 0x10000000
476#define PCI_EXP_DEVCTL 8
477#define PCI_EXP_DEVCTL_BCR_FLR 0x8000
478
479
480
481#include <pci_ids.h>
482
483#ifndef __ASSEMBLY__
484
485#ifdef CONFIG_SYS_PCI_64BIT
486typedef u64 pci_addr_t;
487typedef u64 pci_size_t;
488#else
489typedef u32 pci_addr_t;
490typedef u32 pci_size_t;
491#endif
492
493struct pci_region {
494 pci_addr_t bus_start;
495 phys_addr_t phys_start;
496 pci_size_t size;
497 unsigned long flags;
498
499 pci_addr_t bus_lower;
500};
501
502#define PCI_REGION_MEM 0x00000000
503#define PCI_REGION_IO 0x00000001
504#define PCI_REGION_TYPE 0x00000001
505#define PCI_REGION_PREFETCH 0x00000008
506
507#define PCI_REGION_SYS_MEMORY 0x00000100
508#define PCI_REGION_RO 0x00000200
509
510static inline void pci_set_region(struct pci_region *reg,
511 pci_addr_t bus_start,
512 phys_addr_t phys_start,
513 pci_size_t size,
514 unsigned long flags) {
515 reg->bus_start = bus_start;
516 reg->phys_start = phys_start;
517 reg->size = size;
518 reg->flags = flags;
519}
520
521typedef int pci_dev_t;
522
523#define PCI_BUS(d) (((d) >> 16) & 0xff)
524
525
526
527
528
529
530
531
532
533
534#define PCI_DEV(d) (((d) >> 11) & 0x1f)
535#define PCI_FUNC(d) (((d) >> 8) & 0x7)
536#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
537
538#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
539#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
540#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
541#define PCI_VENDEV(v, d) (((v) << 16) | (d))
542#define PCI_ANY_ID (~0)
543
544struct pci_device_id {
545 unsigned int vendor, device;
546 unsigned int subvendor, subdevice;
547 unsigned int class, class_mask;
548 unsigned long driver_data;
549};
550
551struct pci_controller;
552
553struct pci_config_table {
554 unsigned int vendor, device;
555 unsigned int class;
556 unsigned int bus;
557 unsigned int dev;
558 unsigned int func;
559
560 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
561 struct pci_config_table *);
562 unsigned long priv[3];
563};
564
565extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
566 struct pci_config_table *);
567extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
568 struct pci_config_table *);
569
570#define MAX_PCI_REGIONS 7
571
572#define INDIRECT_TYPE_NO_PCIE_LINK 1
573
574
575
576
577
578
579struct pci_controller {
580#ifdef CONFIG_DM_PCI
581 struct udevice *bus;
582 struct udevice *ctlr;
583#else
584 struct pci_controller *next;
585#endif
586
587 int first_busno;
588 int last_busno;
589
590 volatile unsigned int *cfg_addr;
591 volatile unsigned char *cfg_data;
592
593 int indirect_type;
594
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603
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605 struct pci_region regions[MAX_PCI_REGIONS];
606 int region_count;
607
608 struct pci_config_table *config_table;
609
610 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
611#ifndef CONFIG_DM_PCI
612
613 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
614 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
615 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
616 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
617 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
618 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
619#endif
620
621
622 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
623
624#ifndef CONFIG_DM_PCI
625 int current_busno;
626
627 void *priv_data;
628#endif
629};
630
631#ifndef CONFIG_DM_PCI
632static inline void pci_set_ops(struct pci_controller *hose,
633 int (*read_byte)(struct pci_controller*,
634 pci_dev_t, int where, u8 *),
635 int (*read_word)(struct pci_controller*,
636 pci_dev_t, int where, u16 *),
637 int (*read_dword)(struct pci_controller*,
638 pci_dev_t, int where, u32 *),
639 int (*write_byte)(struct pci_controller*,
640 pci_dev_t, int where, u8),
641 int (*write_word)(struct pci_controller*,
642 pci_dev_t, int where, u16),
643 int (*write_dword)(struct pci_controller*,
644 pci_dev_t, int where, u32)) {
645 hose->read_byte = read_byte;
646 hose->read_word = read_word;
647 hose->read_dword = read_dword;
648 hose->write_byte = write_byte;
649 hose->write_word = write_word;
650 hose->write_dword = write_dword;
651}
652#endif
653
654#ifdef CONFIG_PCI_INDIRECT_BRIDGE
655extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
656#endif
657
658#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
659extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
660 pci_addr_t addr, unsigned long flags);
661extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
662 phys_addr_t addr, unsigned long flags);
663
664#define pci_phys_to_bus(dev, addr, flags) \
665 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
666#define pci_bus_to_phys(dev, addr, flags) \
667 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
668
669#define pci_virt_to_bus(dev, addr, flags) \
670 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
671 (virt_to_phys(addr)), (flags))
672#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
673 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
674 (addr), (flags)), \
675 (len), (map_flags))
676
677#define pci_phys_to_mem(dev, addr) \
678 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
679#define pci_mem_to_phys(dev, addr) \
680 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
681#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
682#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
683
684#define pci_virt_to_mem(dev, addr) \
685 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
686#define pci_mem_to_virt(dev, addr, len, map_flags) \
687 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
688#define pci_virt_to_io(dev, addr) \
689 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
690#define pci_io_to_virt(dev, addr, len, map_flags) \
691 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
692
693
694extern int pci_hose_read_config_byte(struct pci_controller *hose,
695 pci_dev_t dev, int where, u8 *val);
696extern int pci_hose_read_config_word(struct pci_controller *hose,
697 pci_dev_t dev, int where, u16 *val);
698extern int pci_hose_read_config_dword(struct pci_controller *hose,
699 pci_dev_t dev, int where, u32 *val);
700extern int pci_hose_write_config_byte(struct pci_controller *hose,
701 pci_dev_t dev, int where, u8 val);
702extern int pci_hose_write_config_word(struct pci_controller *hose,
703 pci_dev_t dev, int where, u16 val);
704extern int pci_hose_write_config_dword(struct pci_controller *hose,
705 pci_dev_t dev, int where, u32 val);
706#endif
707
708#ifndef CONFIG_DM_PCI
709extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
710extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
711extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
712extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
713extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
714extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
715#endif
716
717void pciauto_region_init(struct pci_region *res);
718void pciauto_region_align(struct pci_region *res, pci_size_t size);
719void pciauto_config_init(struct pci_controller *hose);
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732
733int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
734 pci_addr_t *bar, bool supports_64bit);
735
736#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
737extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
738 pci_dev_t dev, int where, u8 *val);
739extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
740 pci_dev_t dev, int where, u16 *val);
741extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
742 pci_dev_t dev, int where, u8 val);
743extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
744 pci_dev_t dev, int where, u16 val);
745
746extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
747extern void pci_register_hose(struct pci_controller* hose);
748extern struct pci_controller* pci_bus_to_hose(int bus);
749extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
750extern struct pci_controller *pci_get_hose_head(void);
751
752extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
753extern int pci_hose_scan(struct pci_controller *hose);
754extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
755
756extern void pciauto_setup_device(struct pci_controller *hose,
757 pci_dev_t dev, int bars_num,
758 struct pci_region *mem,
759 struct pci_region *prefetch,
760 struct pci_region *io);
761extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
762 pci_dev_t dev, int sub_bus);
763extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
764 pci_dev_t dev, int sub_bus);
765extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
766
767extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
768extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
769pci_dev_t pci_find_class(unsigned int find_class, int index);
770
771extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
772 int cap);
773extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
774 u8 hdr_type);
775extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
776 int cap);
777
778int pci_find_next_ext_capability(struct pci_controller *hose,
779 pci_dev_t dev, int start, int cap);
780int pci_hose_find_ext_capability(struct pci_controller *hose,
781 pci_dev_t dev, int cap);
782
783#ifdef CONFIG_PCI_FIXUP_DEV
784extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
785 unsigned short vendor,
786 unsigned short device,
787 unsigned short class);
788#endif
789#endif
790
791const char * pci_class_str(u8 class);
792int pci_last_busno(void);
793
794#ifdef CONFIG_MPC85xx
795extern void pci_mpc85xx_init (struct pci_controller *hose);
796#endif
797
798#ifdef CONFIG_PCIE_IMX
799extern void imx_pcie_remove(void);
800#endif
801
802#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
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815void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
816 u32 addr);
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826u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
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839pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
840 struct pci_device_id *ids, int *indexp);
841#endif
842
843
844enum pci_size_t {
845 PCI_SIZE_8,
846 PCI_SIZE_16,
847 PCI_SIZE_32,
848};
849
850struct udevice;
851
852#ifdef CONFIG_DM_PCI
853
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865
866struct pci_child_platdata {
867 int devfn;
868 unsigned short vendor;
869 unsigned short device;
870 unsigned int class;
871};
872
873
874struct dm_pci_ops {
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893 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
894 ulong *valuep, enum pci_size_t size);
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904
905 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
906 ulong value, enum pci_size_t size);
907};
908
909
910#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
911
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917
918pci_dev_t dm_pci_get_bdf(struct udevice *dev);
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935int pci_bind_bus_devices(struct udevice *bus);
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950int pci_auto_config_devices(struct udevice *bus);
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959int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
960
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968int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
969 struct udevice **devp);
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982int pci_find_first_device(struct udevice **devp);
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994int pci_find_next_device(struct udevice **devp);
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1003int pci_get_ff(enum pci_size_t size);
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1017int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
1018 int *indexp, struct udevice **devp);
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1029int pci_find_device_id(struct pci_device_id *ids, int index,
1030 struct udevice **devp);
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1046int dm_pci_hose_probe_bus(struct udevice *bus);
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1061int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
1062 unsigned long *valuep, enum pci_size_t size);
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1074int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1075 unsigned long value, enum pci_size_t size);
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1089int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1090 u32 clr, u32 set);
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1095
1096int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
1097 enum pci_size_t size);
1098
1099int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
1100int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
1101int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
1102
1103int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1104 enum pci_size_t size);
1105
1106int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1107int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1108int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
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1114int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1115int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1116int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
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1123int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
1124int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1125int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1126int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1127int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1128int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
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1148int pci_generic_mmap_write_config(
1149 struct udevice *bus,
1150 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1151 pci_dev_t bdf,
1152 uint offset,
1153 ulong value,
1154 enum pci_size_t size);
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1173int pci_generic_mmap_read_config(
1174 struct udevice *bus,
1175 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1176 pci_dev_t bdf,
1177 uint offset,
1178 ulong *valuep,
1179 enum pci_size_t size);
1180
1181#ifdef CONFIG_DM_PCI_COMPAT
1182
1183static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1184 u32 value)
1185{
1186 return pci_write_config32(pcidev, offset, value);
1187}
1188
1189
1190static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1191 u16 value)
1192{
1193 return pci_write_config16(pcidev, offset, value);
1194}
1195
1196
1197static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1198 u8 value)
1199{
1200 return pci_write_config8(pcidev, offset, value);
1201}
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1203
1204static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1205 u32 *valuep)
1206{
1207 return pci_read_config32(pcidev, offset, valuep);
1208}
1209
1210
1211static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1212 u16 *valuep)
1213{
1214 return pci_read_config16(pcidev, offset, valuep);
1215}
1216
1217
1218static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1219 u8 *valuep)
1220{
1221 return pci_read_config8(pcidev, offset, valuep);
1222}
1223#endif
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1234int dm_pciauto_config_device(struct udevice *dev);
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1249ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
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1264ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1265 enum pci_size_t size);
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1273struct udevice *pci_get_controller(struct udevice *dev);
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1284int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1285 struct pci_region **memp, struct pci_region **prefp);
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1296void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
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1305u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
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1315phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1316 unsigned long flags);
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1326pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1327 unsigned long flags);
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1344void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
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1367int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
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1389int dm_pci_find_capability(struct udevice *dev, int cap);
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1414int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
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1437int dm_pci_find_ext_capability(struct udevice *dev, int cap);
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1445int dm_pci_flr(struct udevice *dev);
1446
1447#define dm_pci_virt_to_bus(dev, addr, flags) \
1448 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1449#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1450 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1451 (len), (map_flags))
1452
1453#define dm_pci_phys_to_mem(dev, addr) \
1454 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1455#define dm_pci_mem_to_phys(dev, addr) \
1456 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1457#define dm_pci_phys_to_io(dev, addr) \
1458 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1459#define dm_pci_io_to_phys(dev, addr) \
1460 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1461
1462#define dm_pci_virt_to_mem(dev, addr) \
1463 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1464#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1465 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1466#define dm_pci_virt_to_io(dev, addr) \
1467 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
1468#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
1469 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
1470
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1480int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1481 struct udevice **devp);
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1490
1491int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
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1499
1500struct pci_emul_uc_priv {
1501 struct udevice *client;
1502};
1503
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1507struct dm_pci_emul_ops {
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1517 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
1518 enum pci_size_t size);
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1528 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1529 enum pci_size_t size);
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1540 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1541 enum pci_size_t size);
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1552 int (*write_io)(struct udevice *dev, unsigned int addr,
1553 ulong value, enum pci_size_t size);
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1569 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1570 unsigned long *lenp, void **ptrp);
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1585 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1586 unsigned long len);
1587};
1588
1589
1590#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1591
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1603int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
1604 struct udevice **containerp, struct udevice **emulp);
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1613int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
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1623int pci_get_devfn(struct udevice *dev);
1624
1625#endif
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1636#define PCI_DEVICE(vend, dev) \
1637 .vendor = (vend), .device = (dev), \
1638 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1639
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1650#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1651 .vendor = (vend), .device = (dev), \
1652 .subvendor = (subvend), .subdevice = (subdev)
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1663#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1664 .class = (dev_class), .class_mask = (dev_class_mask), \
1665 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1666 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
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1679#define PCI_VDEVICE(vend, dev) \
1680 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1681 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
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1688struct pci_driver_entry {
1689 struct driver *driver;
1690 const struct pci_device_id *match;
1691};
1692
1693#define U_BOOT_PCI_DEVICE(__name, __match) \
1694 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1695 .driver = llsym(struct driver, __name, driver), \
1696 .match = __match, \
1697 }
1698
1699#endif
1700#endif
1701