1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2017 NXP 4 */ 5 6#ifndef __ASM_ARCH_IMX8M_REGS_H__ 7#define __ASM_ARCH_IMX8M_REGS_H__ 8 9#define ARCH_MXC 10 11#include <asm/mach-imx/regs-lcdif.h> 12 13#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800 14#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800 15 16#define M4_BOOTROM_BASE_ADDR 0x007E0000 17 18#define GPIO1_BASE_ADDR 0X30200000 19#define GPIO2_BASE_ADDR 0x30210000 20#define GPIO3_BASE_ADDR 0x30220000 21#define GPIO4_BASE_ADDR 0x30230000 22#define GPIO5_BASE_ADDR 0x30240000 23#define WDOG1_BASE_ADDR 0x30280000 24#define WDOG2_BASE_ADDR 0x30290000 25#define WDOG3_BASE_ADDR 0x302A0000 26#define IOMUXC_BASE_ADDR 0x30330000 27#define IOMUXC_GPR_BASE_ADDR 0x30340000 28#define OCOTP_BASE_ADDR 0x30350000 29#define ANATOP_BASE_ADDR 0x30360000 30#define CCM_BASE_ADDR 0x30380000 31#define SRC_BASE_ADDR 0x30390000 32#define GPC_BASE_ADDR 0x303A0000 33 34#define SYSCNT_RD_BASE_ADDR 0x306A0000 35#define SYSCNT_CMP_BASE_ADDR 0x306B0000 36#define SYSCNT_CTRL_BASE_ADDR 0x306C0000 37 38#define UART1_BASE_ADDR 0x30860000 39#define UART3_BASE_ADDR 0x30880000 40#define UART2_BASE_ADDR 0x30890000 41#define I2C1_BASE_ADDR 0x30A20000 42#define I2C2_BASE_ADDR 0x30A30000 43#define I2C3_BASE_ADDR 0x30A40000 44#define I2C4_BASE_ADDR 0x30A50000 45#define UART4_BASE_ADDR 0x30A60000 46#define USDHC1_BASE_ADDR 0x30B40000 47#define USDHC2_BASE_ADDR 0x30B50000 48#ifdef CONFIG_IMX8MM 49#define USDHC3_BASE_ADDR 0x30B60000 50#endif 51 52#define TZASC_BASE_ADDR 0x32F80000 53 54#define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \ 55 0x30320000 : 0x32e00000 56 57#define SRC_IPS_BASE_ADDR 0x30390000 58#define SRC_DDRC_RCR_ADDR 0x30391000 59#define SRC_DDRC2_RCR_ADDR 0x30391004 60 61#define DDRC_DDR_SS_GPR0 0x3d000000 62#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) 63#define DDR_CSD1_BASE_ADDR 0x40000000 64 65#if !defined(__ASSEMBLY__) 66#include <asm/types.h> 67#include <linux/bitops.h> 68#include <stdbool.h> 69 70#define GPR_TZASC_EN BIT(0) 71#define GPR_TZASC_EN_LOCK BIT(16) 72 73#define SRC_SCR_M4_ENABLE_OFFSET 3 74#define SRC_SCR_M4_ENABLE_MASK BIT(3) 75#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0 76#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) 77#define SRC_DDR1_ENABLE_MASK 0x8F000000UL 78#define SRC_DDR2_ENABLE_MASK 0x8F000000UL 79#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3) 80#define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2) 81#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) 82#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) 83 84struct iomuxc_gpr_base_regs { 85 u32 gpr[47]; 86}; 87 88struct ocotp_regs { 89 u32 ctrl; 90 u32 ctrl_set; 91 u32 ctrl_clr; 92 u32 ctrl_tog; 93 u32 timing; 94 u32 rsvd0[3]; 95 u32 data; 96 u32 rsvd1[3]; 97 u32 read_ctrl; 98 u32 rsvd2[3]; 99 u32 read_fuse_data; 100 u32 rsvd3[3]; 101 u32 sw_sticky; 102 u32 rsvd4[3]; 103 u32 scs; 104 u32 scs_set; 105 u32 scs_clr; 106 u32 scs_tog; 107 u32 crc_addr; 108 u32 rsvd5[3]; 109 u32 crc_value; 110 u32 rsvd6[3]; 111 u32 version; 112 u32 rsvd7[0xdb]; 113 114 /* fuse banks */ 115 struct fuse_bank { 116 u32 fuse_regs[0x10]; 117 } bank[0]; 118}; 119 120struct fuse_bank0_regs { 121 u32 lock; 122 u32 rsvd0[3]; 123 u32 uid_low; 124 u32 rsvd1[3]; 125 u32 uid_high; 126 u32 rsvd2[7]; 127}; 128 129struct fuse_bank1_regs { 130 u32 tester3; 131 u32 rsvd0[3]; 132 u32 tester4; 133 u32 rsvd1[3]; 134 u32 tester5; 135 u32 rsvd2[3]; 136 u32 cfg0; 137 u32 rsvd3[3]; 138}; 139 140struct fuse_bank3_regs { 141 u32 mem_trim0; 142 u32 rsvd0[3]; 143 u32 mem_trim1; 144 u32 rsvd1[3]; 145 u32 mem_trim2; 146 u32 rsvd2[3]; 147 u32 ana0; 148 u32 rsvd3[3]; 149}; 150 151struct fuse_bank9_regs { 152 u32 mac_addr0; 153 u32 rsvd0[3]; 154 u32 mac_addr1; 155 u32 rsvd1[11]; 156}; 157 158struct fuse_bank38_regs { 159 u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/ 160 u32 rsvd0[3]; 161 u32 ana_trim2; 162 u32 rsvd1[3]; 163 u32 ana_trim3; 164 u32 rsvd2[3]; 165 u32 ana_trim4; 166 u32 rsvd3[3]; 167}; 168 169struct fuse_bank39_regs { 170 u32 ana_trim5; 171 u32 rsvd[15]; 172}; 173 174#ifdef CONFIG_IMX8MQ 175struct anamix_pll { 176 u32 audio_pll1_cfg0; 177 u32 audio_pll1_cfg1; 178 u32 audio_pll2_cfg0; 179 u32 audio_pll2_cfg1; 180 u32 video_pll_cfg0; 181 u32 video_pll_cfg1; 182 u32 gpu_pll_cfg0; 183 u32 gpu_pll_cfg1; 184 u32 vpu_pll_cfg0; 185 u32 vpu_pll_cfg1; 186 u32 arm_pll_cfg0; 187 u32 arm_pll_cfg1; 188 u32 sys_pll1_cfg0; 189 u32 sys_pll1_cfg1; 190 u32 sys_pll1_cfg2; 191 u32 sys_pll2_cfg0; 192 u32 sys_pll2_cfg1; 193 u32 sys_pll2_cfg2; 194 u32 sys_pll3_cfg0; 195 u32 sys_pll3_cfg1; 196 u32 sys_pll3_cfg2; 197 u32 video_pll2_cfg0; 198 u32 video_pll2_cfg1; 199 u32 video_pll2_cfg2; 200 u32 dram_pll_cfg0; 201 u32 dram_pll_cfg1; 202 u32 dram_pll_cfg2; 203 u32 digprog; 204 u32 osc_misc_cfg; 205 u32 pllout_monitor_cfg; 206 u32 frac_pllout_div_cfg; 207 u32 sscg_pllout_div_cfg; 208}; 209#else 210struct anamix_pll { 211 u32 audio_pll1_gnrl_ctl; 212 u32 audio_pll1_fdiv_ctl0; 213 u32 audio_pll1_fdiv_ctl1; 214 u32 audio_pll1_sscg_ctl; 215 u32 audio_pll1_mnit_ctl; 216 u32 audio_pll2_gnrl_ctl; 217 u32 audio_pll2_fdiv_ctl0; 218 u32 audio_pll2_fdiv_ctl1; 219 u32 audio_pll2_sscg_ctl; 220 u32 audio_pll2_mnit_ctl; 221 u32 video_pll1_gnrl_ctl; 222 u32 video_pll1_fdiv_ctl0; 223 u32 video_pll1_fdiv_ctl1; 224 u32 video_pll1_sscg_ctl; 225 u32 video_pll1_mnit_ctl; 226 u32 reserved[5]; 227 u32 dram_pll_gnrl_ctl; 228 u32 dram_pll_fdiv_ctl0; 229 u32 dram_pll_fdiv_ctl1; 230 u32 dram_pll_sscg_ctl; 231 u32 dram_pll_mnit_ctl; 232 u32 gpu_pll_gnrl_ctl; 233 u32 gpu_pll_div_ctl; 234 u32 gpu_pll_locked_ctl1; 235 u32 gpu_pll_mnit_ctl; 236 u32 vpu_pll_gnrl_ctl; 237 u32 vpu_pll_div_ctl; 238 u32 vpu_pll_locked_ctl1; 239 u32 vpu_pll_mnit_ctl; 240 u32 arm_pll_gnrl_ctl; 241 u32 arm_pll_div_ctl; 242 u32 arm_pll_locked_ctl1; 243 u32 arm_pll_mnit_ctl; 244 u32 sys_pll1_gnrl_ctl; 245 u32 sys_pll1_div_ctl; 246 u32 sys_pll1_locked_ctl1; 247 u32 reserved2[24]; 248 u32 sys_pll1_mnit_ctl; 249 u32 sys_pll2_gnrl_ctl; 250 u32 sys_pll2_div_ctl; 251 u32 sys_pll2_locked_ctl1; 252 u32 sys_pll2_mnit_ctl; 253 u32 sys_pll3_gnrl_ctl; 254 u32 sys_pll3_div_ctl; 255 u32 sys_pll3_locked_ctl1; 256 u32 sys_pll3_mnit_ctl; 257 u32 anamix_misc_ctl; 258 u32 anamix_clk_mnit_ctl; 259 u32 reserved3[437]; 260 u32 digprog; 261}; 262#endif 263 264/* System Reset Controller (SRC) */ 265struct src { 266 u32 scr; 267 u32 a53rcr; 268 u32 a53rcr1; 269 u32 m4rcr; 270 u32 reserved1[4]; 271 u32 usbophy1_rcr; 272 u32 usbophy2_rcr; 273 u32 mipiphy_rcr; 274 u32 pciephy_rcr; 275 u32 hdmi_rcr; 276 u32 disp_rcr; 277 u32 reserved2[2]; 278 u32 gpu_rcr; 279 u32 vpu_rcr; 280 u32 pcie2_rcr; 281 u32 mipiphy1_rcr; 282 u32 mipiphy2_rcr; 283 u32 reserved3; 284 u32 sbmr1; 285 u32 srsr; 286 u32 reserved4[2]; 287 u32 sisr; 288 u32 simr; 289 u32 sbmr2; 290 u32 gpr1; 291 u32 gpr2; 292 u32 gpr3; 293 u32 gpr4; 294 u32 gpr5; 295 u32 gpr6; 296 u32 gpr7; 297 u32 gpr8; 298 u32 gpr9; 299 u32 gpr10; 300 u32 reserved5[985]; 301 u32 ddr1_rcr; 302 u32 ddr2_rcr; 303}; 304 305#define WDOG_WDT_MASK BIT(3) 306#define WDOG_WDZST_MASK BIT(0) 307struct wdog_regs { 308 u16 wcr; /* Control */ 309 u16 wsr; /* Service */ 310 u16 wrsr; /* Reset Status */ 311 u16 wicr; /* Interrupt Control */ 312 u16 wmcr; /* Miscellaneous Control */ 313}; 314 315struct bootrom_sw_info { 316 u8 reserved_1; 317 u8 boot_dev_instance; 318 u8 boot_dev_type; 319 u8 reserved_2; 320 u32 core_freq; 321 u32 axi_freq; 322 u32 ddr_freq; 323 u32 tick_freq; 324 u32 reserved_3[3]; 325}; 326 327#define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\ 328 0x000009e8) 329#define ROM_SW_INFO_ADDR_A0 0x000009e8 330 331#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \ 332 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \ 333 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0 334 335struct gpc_reg { 336 u32 lpcr_bsc; 337 u32 lpcr_ad; 338 u32 lpcr_cpu1; 339 u32 lpcr_cpu2; 340 u32 lpcr_cpu3; 341 u32 slpcr; 342 u32 mst_cpu_mapping; 343 u32 mmdc_cpu_mapping; 344 u32 mlpcr; 345 u32 pgc_ack_sel; 346 u32 pgc_ack_sel_m4; 347 u32 gpc_misc; 348 u32 imr1_core0; 349 u32 imr2_core0; 350 u32 imr3_core0; 351 u32 imr4_core0; 352 u32 imr1_core1; 353 u32 imr2_core1; 354 u32 imr3_core1; 355 u32 imr4_core1; 356 u32 imr1_cpu1; 357 u32 imr2_cpu1; 358 u32 imr3_cpu1; 359 u32 imr4_cpu1; 360 u32 imr1_cpu3; 361 u32 imr2_cpu3; 362 u32 imr3_cpu3; 363 u32 imr4_cpu3; 364 u32 isr1_cpu0; 365 u32 isr2_cpu0; 366 u32 isr3_cpu0; 367 u32 isr4_cpu0; 368 u32 isr1_cpu1; 369 u32 isr2_cpu1; 370 u32 isr3_cpu1; 371 u32 isr4_cpu1; 372 u32 isr1_cpu2; 373 u32 isr2_cpu2; 374 u32 isr3_cpu2; 375 u32 isr4_cpu2; 376 u32 isr1_cpu3; 377 u32 isr2_cpu3; 378 u32 isr3_cpu3; 379 u32 isr4_cpu3; 380 u32 slt0_cfg; 381 u32 slt1_cfg; 382 u32 slt2_cfg; 383 u32 slt3_cfg; 384 u32 slt4_cfg; 385 u32 slt5_cfg; 386 u32 slt6_cfg; 387 u32 slt7_cfg; 388 u32 slt8_cfg; 389 u32 slt9_cfg; 390 u32 slt10_cfg; 391 u32 slt11_cfg; 392 u32 slt12_cfg; 393 u32 slt13_cfg; 394 u32 slt14_cfg; 395 u32 pgc_cpu_0_1_mapping; 396 u32 cpu_pgc_up_trg; 397 u32 mix_pgc_up_trg; 398 u32 pu_pgc_up_trg; 399 u32 cpu_pgc_dn_trg; 400 u32 mix_pgc_dn_trg; 401 u32 pu_pgc_dn_trg; 402 u32 lpcr_bsc2; 403 u32 pgc_cpu_2_3_mapping; 404 u32 lps_cpu0; 405 u32 lps_cpu1; 406 u32 lps_cpu2; 407 u32 lps_cpu3; 408 u32 gpc_gpr; 409 u32 gtor; 410 u32 debug_addr1; 411 u32 debug_addr2; 412 u32 cpu_pgc_up_status1; 413 u32 mix_pgc_up_status0; 414 u32 mix_pgc_up_status1; 415 u32 mix_pgc_up_status2; 416 u32 m4_mix_pgc_up_status0; 417 u32 m4_mix_pgc_up_status1; 418 u32 m4_mix_pgc_up_status2; 419 u32 pu_pgc_up_status0; 420 u32 pu_pgc_up_status1; 421 u32 pu_pgc_up_status2; 422 u32 m4_pu_pgc_up_status0; 423 u32 m4_pu_pgc_up_status1; 424 u32 m4_pu_pgc_up_status2; 425 u32 a53_lp_io_0; 426 u32 a53_lp_io_1; 427 u32 a53_lp_io_2; 428 u32 cpu_pgc_dn_status1; 429 u32 mix_pgc_dn_status0; 430 u32 mix_pgc_dn_status1; 431 u32 mix_pgc_dn_status2; 432 u32 m4_mix_pgc_dn_status0; 433 u32 m4_mix_pgc_dn_status1; 434 u32 m4_mix_pgc_dn_status2; 435 u32 pu_pgc_dn_status0; 436 u32 pu_pgc_dn_status1; 437 u32 pu_pgc_dn_status2; 438 u32 m4_pu_pgc_dn_status0; 439 u32 m4_pu_pgc_dn_status1; 440 u32 m4_pu_pgc_dn_status2; 441 u32 res[3]; 442 u32 mix_pdn_flg; 443 u32 pu_pdn_flg; 444 u32 m4_mix_pdn_flg; 445 u32 m4_pu_pdn_flg; 446 u32 imr1_core2; 447 u32 imr2_core2; 448 u32 imr3_core2; 449 u32 imr4_core2; 450 u32 imr1_core3; 451 u32 imr2_core3; 452 u32 imr3_core3; 453 u32 imr4_core3; 454 u32 pgc_ack_sel_pu; 455 u32 pgc_ack_sel_m4_pu; 456 u32 slt15_cfg; 457 u32 slt16_cfg; 458 u32 slt17_cfg; 459 u32 slt18_cfg; 460 u32 slt19_cfg; 461 u32 gpc_pu_pwrhsk; 462 u32 slt0_cfg_pu; 463 u32 slt1_cfg_pu; 464 u32 slt2_cfg_pu; 465 u32 slt3_cfg_pu; 466 u32 slt4_cfg_pu; 467 u32 slt5_cfg_pu; 468 u32 slt6_cfg_pu; 469 u32 slt7_cfg_pu; 470 u32 slt8_cfg_pu; 471 u32 slt9_cfg_pu; 472 u32 slt10_cfg_pu; 473 u32 slt11_cfg_pu; 474 u32 slt12_cfg_pu; 475 u32 slt13_cfg_pu; 476 u32 slt14_cfg_pu; 477 u32 slt15_cfg_pu; 478 u32 slt16_cfg_pu; 479 u32 slt17_cfg_pu; 480 u32 slt18_cfg_pu; 481 u32 slt19_cfg_pu; 482}; 483 484struct pgc_reg { 485 u32 pgcr; 486 u32 pgpupscr; 487 u32 pgpdnscr; 488 u32 pgsr; 489 u32 pgauxsw; 490 u32 pgdr; 491}; 492#endif 493#endif 494