LXR uboot/arch/arm/include/asm/global

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2002-2010
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 */
   6
   7#ifndef __ASM_GBL_DATA_H
   8#define __ASM_GBL_DATA_H
   9
  10/* Architecture-specific global data */
  11struct arch_global_data {
  12#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
  13        u32 sdhc_clk;
  14#endif
  15
  16#if defined(CONFIG_FSL_ESDHC)
  17        u32 sdhc_per_clk;
  18#endif
  19
  20#if defined(CONFIG_U_QE)
  21        u32 qe_clk;
  22        u32 brg_clk;
  23        uint mp_alloc_base;
  24        uint mp_alloc_top;
  25#endif /* CONFIG_U_QE */
  26
  27#ifdef CONFIG_AT91FAMILY
  28        /* "static data" needed by at91's clock.c */
  29        unsigned long   cpu_clk_rate_hz;
  30        unsigned long   main_clk_rate_hz;
  31        unsigned long   mck_rate_hz;
  32        unsigned long   plla_rate_hz;
  33        unsigned long   pllb_rate_hz;
  34        unsigned long   at91_pllb_usb_init;
  35#endif
  36        /* "static data" needed by most of timer.c on ARM platforms */
  37        unsigned long timer_rate_hz;
  38        unsigned int tbu;
  39        unsigned int tbl;
  40        unsigned long lastinc;
  41        unsigned long long timer_reset_value;
  42#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  43        unsigned long tlb_addr;
  44        unsigned long tlb_size;
  45#if defined(CONFIG_ARM64)
  46        unsigned long tlb_fillptr;
  47        unsigned long tlb_emerg;
  48#endif
  49#endif
  50#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  51#define MEM_RESERVE_SECURE_SECURED      0x1
  52#define MEM_RESERVE_SECURE_MAINTAINED   0x2
  53#define MEM_RESERVE_SECURE_ADDR_MASK    (~0x3)
  54        /*
  55         * Secure memory addr
  56         * This variable needs maintenance if the RAM base is not zero,
  57         * or if RAM splits into non-consecutive banks. It also has a
  58         * flag indicating the secure memory is marked as secure by MMU.
  59         * Flags used: 0x1 secured
  60         *             0x2 maintained
  61         */
  62        phys_addr_t secure_ram;
  63        unsigned long tlb_allocated;
  64#endif
  65#ifdef CONFIG_RESV_RAM
  66        /*
  67         * Reserved RAM for memory resident, eg. Management Complex (MC)
  68         * driver which continues to run after U-Boot exits.
  69         */
  70        phys_addr_t resv_ram;
  71#endif
  72
  73#ifdef CONFIG_ARCH_OMAP2PLUS
  74        u32 omap_boot_device;
  75        u32 omap_boot_mode;
  76        u8 omap_ch_flags;
  77#endif
  78#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
  79        unsigned long mem2_clk;
  80#endif
  81
  82#ifdef CONFIG_ARCH_IMX8
  83        struct udevice *scu_dev;
  84#endif
  85};
  86
  87#include <asm-generic/global_data.h>
  88
  89#ifdef __clang__
  90
  91#define DECLARE_GLOBAL_DATA_PTR
  92#define gd      get_gd()
  93
  94static inline gd_t *get_gd(void)
  95{
  96        gd_t *gd_ptr;
  97
  98#ifdef CONFIG_ARM64
  99        __asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr));
 100#else
 101        __asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr));
 102#endif
 103
 104        return gd_ptr;
 105}
 106
 107#else
 108
 109#ifdef CONFIG_ARM64
 110#define DECLARE_GLOBAL_DATA_PTR         register volatile gd_t *gd asm ("x18")
 111#else
 112#define DECLARE_GLOBAL_DATA_PTR         register volatile gd_t *gd asm ("r9")
 113#endif
 114#endif
 115
 116static inline void set_gd(volatile gd_t *gd_ptr)
 117{
 118#ifdef CONFIG_ARM64
 119        __asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr));
 120#else
 121        __asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr));
 122#endif
 123}
 124
 125#endif /* __ASM_GBL_DATA_H */
 126