1
2
3
4
5#include <common.h>
6#include <dm.h>
7#include <regmap.h>
8#include <syscon.h>
9#include <asm/gic.h>
10#include <asm/gic-v3.h>
11#include <asm/io.h>
12#include <linux/bitops.h>
13#include <linux/sizes.h>
14
15static u32 lpi_id_bits;
16
17#define LPI_NRBITS lpi_id_bits
18#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
19#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
20
21
22#define MAX_GIC_REDISTRIBUTORS 8
23
24
25
26
27
28
29
30
31
32struct gic_v3_its_priv {
33 ulong gicd_base;
34 ulong gicr_base;
35 ulong lpi_base;
36 u32 num_redist;
37};
38
39static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
40{
41 struct udevice *dev;
42 fdt_addr_t addr;
43 int ret;
44
45 ret = uclass_get_device_by_driver(UCLASS_IRQ,
46 DM_GET_DRIVER(arm_gic_v3_its), &dev);
47 if (ret) {
48 pr_err("%s: failed to get %s irq device\n", __func__,
49 DM_GET_DRIVER(arm_gic_v3_its)->name);
50 return ret;
51 }
52
53 addr = dev_read_addr_index(dev, 0);
54 if (addr == FDT_ADDR_T_NONE) {
55 pr_err("%s: failed to get GICD address\n", __func__);
56 return -EINVAL;
57 }
58 priv->gicd_base = addr;
59
60 addr = dev_read_addr_index(dev, 1);
61 if (addr == FDT_ADDR_T_NONE) {
62 pr_err("%s: failed to get GICR address\n", __func__);
63 return -EINVAL;
64 }
65 priv->gicr_base = addr;
66
67 return 0;
68}
69
70static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
71{
72 struct regmap *regmap;
73 struct udevice *dev;
74 int ret;
75
76 ret = uclass_get_device_by_driver(UCLASS_SYSCON,
77 DM_GET_DRIVER(gic_lpi_syscon), &dev);
78 if (ret) {
79 pr_err("%s: failed to get %s syscon device\n", __func__,
80 DM_GET_DRIVER(gic_lpi_syscon)->name);
81 return ret;
82 }
83
84 regmap = syscon_get_regmap(dev);
85 if (!regmap) {
86 pr_err("%s: failed to regmap for %s syscon device\n", __func__,
87 DM_GET_DRIVER(gic_lpi_syscon)->name);
88 return -ENODEV;
89 }
90 priv->lpi_base = regmap->ranges[0].start;
91
92 priv->num_redist = dev_read_u32_default(dev, "max-gic-redistributors",
93 MAX_GIC_REDISTRIBUTORS);
94
95 return 0;
96}
97
98
99
100
101
102int gic_lpi_tables_init(void)
103{
104 struct gic_v3_its_priv priv;
105 u32 gicd_typer;
106 u64 val;
107 u64 tmp;
108 int i;
109 u64 redist_lpi_base;
110 u64 pend_base;
111
112 if (gic_v3_its_get_gic_addr(&priv))
113 return -EINVAL;
114
115 if (gic_v3_its_get_gic_lpi_addr(&priv))
116 return -EINVAL;
117
118 gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
119
120 if (!(gicd_typer & GICD_TYPER_LPIS)) {
121 pr_err("GIC implementation does not support LPI's\n");
122 return -EINVAL;
123 }
124
125
126
127
128
129
130 for (i = 0; i < priv.num_redist; i++) {
131 u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
132
133 if ((readl((uintptr_t)(priv.gicr_base + offset))) &
134 GICR_CTLR_ENABLE_LPIS) {
135 pr_err("Re-Distributor %d LPI is already enabled\n",
136 i);
137 return -EINVAL;
138 }
139 }
140
141
142 lpi_id_bits = min_t(u32, GICD_TYPER_ID_BITS(gicd_typer),
143 ITS_MAX_LPI_NRBITS);
144
145
146 val = (priv.lpi_base |
147 GICR_PROPBASER_INNERSHAREABLE |
148 GICR_PROPBASER_RAWAWB |
149 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
150
151 writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
152 tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
153 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
154 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
155 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
156 GICR_PROPBASER_CACHEABILITY_MASK);
157 val |= GICR_PROPBASER_NC;
158 writeq(val,
159 (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
160 }
161 }
162
163 redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ;
164
165 pend_base = priv.gicr_base + GICR_PENDBASER;
166 for (i = 0; i < priv.num_redist; i++) {
167 u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
168
169 val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
170 GICR_PENDBASER_INNERSHAREABLE |
171 GICR_PENDBASER_RAWAWB);
172
173 writeq(val, (uintptr_t)(pend_base + offset));
174 tmp = readq((uintptr_t)(pend_base + offset));
175 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
176 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
177 GICR_PENDBASER_CACHEABILITY_MASK);
178 val |= GICR_PENDBASER_NC;
179 writeq(val, (uintptr_t)(pend_base + offset));
180 }
181
182
183 writel(GICR_CTLR_ENABLE_LPIS,
184 (uintptr_t)(priv.gicr_base + offset));
185 }
186
187 return 0;
188}
189
190static const struct udevice_id gic_v3_its_ids[] = {
191 { .compatible = "arm,gic-v3" },
192 {}
193};
194
195U_BOOT_DRIVER(arm_gic_v3_its) = {
196 .name = "gic-v3",
197 .id = UCLASS_IRQ,
198 .of_match = gic_v3_its_ids,
199};
200
201static const struct udevice_id gic_lpi_syscon_ids[] = {
202 { .compatible = "gic-lpi-base" },
203 {}
204};
205
206U_BOOT_DRIVER(gic_lpi_syscon) = {
207 .name = "gic-lpi-base",
208 .id = UCLASS_SYSCON,
209 .of_match = gic_lpi_syscon_ids,
210};
211
