uboot/arch/arm/mach-meson/board-gx.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
   4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
   5 */
   6
   7#include <common.h>
   8#include <init.h>
   9#include <net.h>
  10#include <asm/arch/boot.h>
  11#include <asm/arch/eth.h>
  12#include <asm/arch/gx.h>
  13#include <asm/arch/mem.h>
  14#include <asm/arch/meson-vpu.h>
  15#include <asm/io.h>
  16#include <asm/armv8/mmu.h>
  17#include <linux/sizes.h>
  18#include <usb.h>
  19#include <linux/usb/otg.h>
  20#include <asm/arch/usb-gx.h>
  21#include <usb/dwc2_udc.h>
  22#include <clk.h>
  23#include <phy.h>
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27int meson_get_boot_device(void)
  28{
  29        return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
  30}
  31
  32/* Configure the reserved memory zones exported by the secure registers
  33 * into EFI and DTB reserved memory entries.
  34 */
  35void meson_init_reserved_memory(void *fdt)
  36{
  37        u64 bl31_size, bl31_start;
  38        u64 bl32_size, bl32_start;
  39        u32 reg;
  40
  41        /*
  42         * Get ARM Trusted Firmware reserved memory zones in :
  43         * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  44         * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  45         * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  46         */
  47        reg = readl(GX_AO_SEC_GP_CFG3);
  48
  49        bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
  50                        >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  51        bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  52
  53        bl31_start = readl(GX_AO_SEC_GP_CFG5);
  54        bl32_start = readl(GX_AO_SEC_GP_CFG4);
  55
  56        /*
  57         * Early Meson GX Firmware revisions did not provide the reserved
  58         * memory zones in the registers, keep fixed memory zone handling.
  59         */
  60        if (IS_ENABLED(CONFIG_MESON_GX) &&
  61            !reg && !bl31_start && !bl32_start) {
  62                bl31_start = 0x10000000;
  63                bl31_size = 0x200000;
  64        }
  65
  66        /* Add first 16MiB reserved zone */
  67        meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
  68
  69        /* Add BL31 reserved zone */
  70        if (bl31_start && bl31_size)
  71                meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  72
  73        /* Add BL32 reserved zone */
  74        if (bl32_start && bl32_size)
  75                meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  76
  77#if defined(CONFIG_VIDEO_MESON)
  78        meson_vpu_rsv_fb(fdt);
  79#endif
  80}
  81
  82phys_size_t get_effective_memsize(void)
  83{
  84        /* Size is reported in MiB, convert it in bytes */
  85        return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
  86                        >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
  87}
  88
  89static struct mm_region gx_mem_map[] = {
  90        {
  91                .virt = 0x0UL,
  92                .phys = 0x0UL,
  93                .size = 0xc0000000UL,
  94                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  95                         PTE_BLOCK_INNER_SHARE
  96        }, {
  97                .virt = 0xc0000000UL,
  98                .phys = 0xc0000000UL,
  99                .size = 0x30000000UL,
 100                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 101                         PTE_BLOCK_NON_SHARE |
 102                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
 103        }, {
 104                /* List terminator */
 105                0,
 106        }
 107};
 108
 109struct mm_region *mem_map = gx_mem_map;
 110
 111/* Configure the Ethernet MAC with the requested interface mode
 112 * with some optional flags.
 113 */
 114void meson_eth_init(phy_interface_t mode, unsigned int flags)
 115{
 116        switch (mode) {
 117        case PHY_INTERFACE_MODE_RGMII:
 118        case PHY_INTERFACE_MODE_RGMII_ID:
 119        case PHY_INTERFACE_MODE_RGMII_RXID:
 120        case PHY_INTERFACE_MODE_RGMII_TXID:
 121                /* Set RGMII mode */
 122                setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
 123                             GX_ETH_REG_0_TX_PHASE(1) |
 124                             GX_ETH_REG_0_TX_RATIO(4) |
 125                             GX_ETH_REG_0_PHY_CLK_EN |
 126                             GX_ETH_REG_0_CLK_EN);
 127
 128                /* Reset to external PHY */
 129                if(!IS_ENABLED(CONFIG_MESON_GXBB))
 130                        writel(0x2009087f, GX_ETH_REG_3);
 131
 132                break;
 133
 134        case PHY_INTERFACE_MODE_RMII:
 135                /* Set RMII mode */
 136                out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
 137                                         GX_ETH_REG_0_CLK_EN);
 138
 139                /* Use GXL RMII Internal PHY (also on GXM) */
 140                if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
 141                        if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
 142                                writel(0x10110181, GX_ETH_REG_2);
 143                                writel(0xe40908ff, GX_ETH_REG_3);
 144                        } else
 145                                writel(0x2009087f, GX_ETH_REG_3);
 146                }
 147
 148                break;
 149
 150        default:
 151                printf("Invalid Ethernet interface mode\n");
 152                return;
 153        }
 154
 155        /* Enable power gate */
 156        clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
 157}
 158
 159#if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
 160        CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
 161static struct dwc2_plat_otg_data meson_gx_dwc2_data;
 162
 163int board_usb_init(int index, enum usb_init_type init)
 164{
 165        struct fdtdec_phandle_args args;
 166        const void *blob = gd->fdt_blob;
 167        int node, dwc2_node;
 168        struct udevice *dev, *clk_dev;
 169        struct clk clk;
 170        int ret;
 171
 172        /* find the usb glue node */
 173        node = fdt_node_offset_by_compatible(blob, -1,
 174                                             "amlogic,meson-gxl-usb-ctrl");
 175        if (node < 0) {
 176                node = fdt_node_offset_by_compatible(blob, -1,
 177                                        "amlogic,meson-gxm-usb-ctrl");
 178                if (node < 0) {
 179                        debug("Not found usb-control node\n");
 180                        return -ENODEV;
 181                }
 182        }
 183
 184        if (!fdtdec_get_is_enabled(blob, node)) {
 185                debug("usb is disabled in the device tree\n");
 186                return -ENODEV;
 187        }
 188
 189        ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
 190        if (ret) {
 191                debug("Not found usb-control device\n");
 192                return ret;
 193        }
 194
 195        /* find the dwc2 node */
 196        dwc2_node = fdt_node_offset_by_compatible(blob, node,
 197                                                  "amlogic,meson-g12a-usb");
 198        if (dwc2_node < 0) {
 199                debug("Not found dwc2 node\n");
 200                return -ENODEV;
 201        }
 202
 203        if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
 204                debug("dwc2 is disabled in the device tree\n");
 205                return -ENODEV;
 206        }
 207
 208        meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
 209        if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
 210                debug("usbotg: can't get base address\n");
 211                return -ENODATA;
 212        }
 213
 214        /* Enable clock */
 215        ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
 216                                             "#clock-cells", 0, 0, &args);
 217        if (ret) {
 218                debug("usbotg has no clocks defined in the device tree\n");
 219                return ret;
 220        }
 221
 222        ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
 223        if (ret)
 224                return ret;
 225
 226        if (args.args_count != 1) {
 227                debug("Can't find clock ID in the device tree\n");
 228                return -ENODATA;
 229        }
 230
 231        clk.dev = clk_dev;
 232        clk.id = args.args[0];
 233
 234        ret = clk_enable(&clk);
 235        if (ret) {
 236                debug("Failed to enable usbotg clock\n");
 237                return ret;
 238        }
 239
 240        meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
 241                                                     "g-rx-fifo-size", 0);
 242        meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
 243                                                        "g-np-tx-fifo-size", 0);
 244        meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
 245                                                     "g-tx-fifo-size", 0);
 246
 247        /* Switch to peripheral mode */
 248        ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
 249        if (ret)
 250                return ret;
 251
 252        return dwc2_udc_probe(&meson_gx_dwc2_data);
 253}
 254
 255int board_usb_cleanup(int index, enum usb_init_type init)
 256{
 257        const void *blob = gd->fdt_blob;
 258        struct udevice *dev;
 259        int node;
 260        int ret;
 261
 262        /* find the usb glue node */
 263        node = fdt_node_offset_by_compatible(blob, -1,
 264                                             "amlogic,meson-gxl-usb-ctrl");
 265        if (node < 0) {
 266                node = fdt_node_offset_by_compatible(blob, -1,
 267                                        "amlogic,meson-gxm-usb-ctrl");
 268                if (node < 0) {
 269                        debug("Not found usb-control node\n");
 270                        return -ENODEV;
 271                }
 272        }
 273
 274        if (!fdtdec_get_is_enabled(blob, node))
 275                return -ENODEV;
 276
 277        ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
 278        if (ret)
 279                return ret;
 280
 281        /* Switch to OTG mode */
 282        ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
 283        if (ret)
 284                return ret;
 285
 286        return 0;
 287}
 288#endif
 289
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.