LXR uboot/arch/arm/mach-mvebu/include/mach/cpu.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2009
   4 * Marvell Semiconductor <www.marvell.com>
   5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   6 */
   7
   8#ifndef _MVEBU_CPU_H
   9#define _MVEBU_CPU_H
  10
  11#include <asm/system.h>
  12
  13#ifndef __ASSEMBLY__
  14
  15#define MVEBU_REG_PCIE_DEVID            (MVEBU_REG_PCIE_BASE + 0x00)
  16#define MVEBU_REG_PCIE_REVID            (MVEBU_REG_PCIE_BASE + 0x08)
  17
  18enum memory_bank {
  19        BANK0,
  20        BANK1,
  21        BANK2,
  22        BANK3
  23};
  24
  25enum cpu_winen {
  26        CPU_WIN_DISABLE,
  27        CPU_WIN_ENABLE
  28};
  29
  30enum cpu_target {
  31        CPU_TARGET_DRAM = 0x0,
  32        CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
  33        CPU_TARGET_ETH23 = 0x3,
  34        CPU_TARGET_PCIE02 = 0x4,
  35        CPU_TARGET_ETH01 = 0x7,
  36        CPU_TARGET_PCIE13 = 0x8,
  37        CPU_TARGET_DFX = 0x8,
  38        CPU_TARGET_SASRAM = 0x9,
  39        CPU_TARGET_SATA01 = 0xa, /* A38X */
  40        CPU_TARGET_NAND = 0xd,
  41        CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
  42};
  43
  44enum cpu_attrib {
  45        CPU_ATTR_SASRAM = 0x01,
  46        CPU_ATTR_DRAM_CS0 = 0x0e,
  47        CPU_ATTR_DRAM_CS1 = 0x0d,
  48        CPU_ATTR_DRAM_CS2 = 0x0b,
  49        CPU_ATTR_DRAM_CS3 = 0x07,
  50        CPU_ATTR_NANDFLASH = 0x2f,
  51        CPU_ATTR_SPIFLASH = 0x1e,
  52        CPU_ATTR_SPI0_CS0 = 0x1e,
  53        CPU_ATTR_SPI0_CS1 = 0x5e,
  54        CPU_ATTR_SPI1_CS2 = 0x9a,
  55        CPU_ATTR_BOOTROM = 0x1d,
  56        CPU_ATTR_PCIE_IO = 0xe0,
  57        CPU_ATTR_PCIE_MEM = 0xe8,
  58        CPU_ATTR_DEV_CS0 = 0x3e,
  59        CPU_ATTR_DEV_CS1 = 0x3d,
  60        CPU_ATTR_DEV_CS2 = 0x3b,
  61        CPU_ATTR_DEV_CS3 = 0x37,
  62};
  63
  64enum {
  65        MVEBU_SOC_AXP,
  66        MVEBU_SOC_A375,
  67        MVEBU_SOC_A38X,
  68        MVEBU_SOC_MSYS,
  69        MVEBU_SOC_UNKNOWN,
  70};
  71
  72#define MVEBU_SDRAM_SIZE_MAX    0xc0000000
  73
  74/*
  75 * Default Device Address MAP BAR values
  76 */
  77#define MBUS_PCI_MEM_BASE       MVEBU_SDRAM_SIZE_MAX
  78#define MBUS_PCI_MEM_SIZE       (128 << 20)
  79#define MBUS_PCI_IO_BASE        0xF1100000
  80#define MBUS_PCI_IO_SIZE        (64 << 10)
  81#define MBUS_SPI_BASE           0xF4000000
  82#define MBUS_SPI_SIZE           (8 << 20)
  83#define MBUS_DFX_BASE           0xF6000000
  84#define MBUS_DFX_SIZE           (1 << 20)
  85#define MBUS_BOOTROM_BASE       0xF8000000
  86#define MBUS_BOOTROM_SIZE       (8 << 20)
  87
  88struct mbus_win {
  89        u32 base;
  90        u32 size;
  91        u8 target;
  92        u8 attr;
  93};
  94
  95/*
  96 * System registers
  97 * Ref: Datasheet sec:A.28
  98 */
  99struct mvebu_system_registers {
 100#if defined(CONFIG_ARMADA_375)
 101        u8 pad1[0x54];
 102#else
 103        u8 pad1[0x60];
 104#endif
 105        u32 rstoutn_mask; /* 0x60 */
 106        u32 sys_soft_rst; /* 0x64 */
 107};
 108
 109/*
 110 * GPIO Registers
 111 * Ref: Datasheet sec:A.19
 112 */
 113struct kwgpio_registers {
 114        u32 dout;
 115        u32 oe;
 116        u32 blink_en;
 117        u32 din_pol;
 118        u32 din;
 119        u32 irq_cause;
 120        u32 irq_mask;
 121        u32 irq_level;
 122};
 123
 124struct sar_freq_modes {
 125        u8 val;
 126        u8 ffc;         /* Fabric Frequency Configuration */
 127        u32 p_clk;
 128        u32 nb_clk;
 129        u32 d_clk;
 130};
 131
 132/* Needed for dynamic (board-specific) mbus configuration */
 133extern struct mvebu_mbus_state mbus_state;
 134
 135/*
 136 * functions
 137 */
 138unsigned int mvebu_sdram_bar(enum memory_bank bank);
 139unsigned int mvebu_sdram_bs(enum memory_bank bank);
 140void mvebu_sdram_size_adjust(enum memory_bank bank);
 141int mvebu_mbus_probe(struct mbus_win windows[], int count);
 142int mvebu_soc_family(void);
 143u32 mvebu_get_nand_clock(void);
 144
 145void return_to_bootrom(void);
 146
 147#ifndef CONFIG_DM_MMC
 148int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
 149#endif
 150
 151void get_sar_freq(struct sar_freq_modes *sar_freq);
 152
 153/*
 154 * Highspeed SERDES PHY config init, ported from bin_hdr
 155 * to mainline U-Boot
 156 */
 157int serdes_phy_config(void);
 158
 159/*
 160 * DDR3 init / training code ported from Marvell bin_hdr. Now
 161 * available in mainline U-Boot in:
 162 * drivers/ddr/marvell
 163 */
 164int ddr3_init(void);
 165
 166/* Auto Voltage Scaling */
 167#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
 168void mv_avs_init(void);
 169void mv_rtc_config(void);
 170#else
 171static inline void mv_avs_init(void) {}
 172static inline void mv_rtc_config(void) {}
 173#endif
 174
 175/* A8K dram functions */
 176u64 a8k_dram_scan_ap_sz(void);
 177int a8k_dram_init_banksize(void);
 178
 179/* A3700 dram functions */
 180int a3700_dram_init(void);
 181int a3700_dram_init_banksize(void);
 182
 183/* A3700 PCIe regions fixer for device tree */
 184int a3700_fdt_fix_pcie_regions(void *blob);
 185
 186/*
 187 * get_ref_clk
 188 *
 189 * return: reference clock in MHz (25 or 40)
 190 */
 191u32 get_ref_clk(void);
 192
 193#endif /* __ASSEMBLY__ */
 194#endif /* _MVEBU_CPU_H */
 195