LXR uboot/arch/arm/mach-omap2/sata.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * TI SATA platform driver
   4 *
   5 * (C) Copyright 2013
   6 * Texas Instruments, <www.ti.com>
   7 */
   8
   9#include <common.h>
  10#include <ahci.h>
  11#include <scsi.h>
  12#include <asm/arch/clock.h>
  13#include <asm/arch/sata.h>
  14#include <sata.h>
  15#include <asm/io.h>
  16#include "pipe3-phy.h"
  17
  18static struct pipe3_dpll_map dpll_map_sata[] = {
  19        {12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
  20        {16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
  21        {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
  22        {20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
  23        {26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
  24        {38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
  25        { },                                    /* Terminator */
  26};
  27
  28struct omap_pipe3 sata_phy = {
  29        .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
  30        /* .power_reg is updated at runtime */
  31        .dpll_map = dpll_map_sata,
  32};
  33
  34int init_sata(int dev)
  35{
  36        int ret;
  37        u32 val;
  38
  39        sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
  40
  41        /* Power up the PHY */
  42        phy_pipe3_power_on(&sata_phy);
  43
  44        /* Enable SATA module, No Idle, No Standby */
  45        val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
  46        writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
  47
  48        ret = ahci_init((void __iomem *)DWC_AHSATA_BASE);
  49
  50        return ret;
  51}
  52
  53int reset_sata(int dev)
  54{
  55        return 0;
  56}
  57
  58/* On OMAP platforms SATA provides the SCSI subsystem */
  59void scsi_init(void)
  60{
  61        init_sata(0);
  62        scsi_scan(1);
  63}
  64
  65int scsi_bus_reset(struct udevice *dev)
  66{
  67        ahci_reset((void __iomem *)DWC_AHSATA_BASE);
  68        ahci_init((void __iomem *)DWC_AHSATA_BASE);
  69
  70        return 0;
  71}
  72