LXR uboot/arch/arm/mach-zynq/cpu.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
   4 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
   5 */
   6#include <common.h>
   7#include <cpu_func.h>
   8#include <init.h>
   9#include <zynqpl.h>
  10#include <asm/cache.h>
  11#include <asm/io.h>
  12#include <asm/arch/clk.h>
  13#include <asm/arch/hardware.h>
  14#include <asm/arch/ps7_init_gpl.h>
  15#include <asm/arch/sys_proto.h>
  16
  17#define ZYNQ_SILICON_VER_MASK   0xF0000000
  18#define ZYNQ_SILICON_VER_SHIFT  28
  19
  20#if CONFIG_IS_ENABLED(FPGA)
  21xilinx_desc fpga = {
  22        .family = xilinx_zynq,
  23        .iface = devcfg,
  24        .operations = &zynq_op,
  25};
  26#endif
  27
  28static const struct {
  29        u8 idcode;
  30#if defined(CONFIG_FPGA)
  31        u32 fpga_size;
  32#endif
  33        char *devicename;
  34} zynq_fpga_descs[] = {
  35        ZYNQ_DESC(7Z007S),
  36        ZYNQ_DESC(7Z010),
  37        ZYNQ_DESC(7Z012S),
  38        ZYNQ_DESC(7Z014S),
  39        ZYNQ_DESC(7Z015),
  40        ZYNQ_DESC(7Z020),
  41        ZYNQ_DESC(7Z030),
  42        ZYNQ_DESC(7Z035),
  43        ZYNQ_DESC(7Z045),
  44        ZYNQ_DESC(7Z100),
  45        { /* Sentinel */ },
  46};
  47
  48int arch_cpu_init(void)
  49{
  50        zynq_slcr_unlock();
  51#ifndef CONFIG_SPL_BUILD
  52        /* Device config APB, unlock the PCAP */
  53        writel(0x757BDF0D, &devcfg_base->unlock);
  54        writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
  55
  56#if (CONFIG_SYS_SDRAM_BASE == 0)
  57        /* remap DDR to zero, FILTERSTART */
  58        writel(0, &scu_base->filter_start);
  59
  60        /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
  61        writel(0x1F, &slcr_base->ocm_cfg);
  62        /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
  63        writel(0x0, &slcr_base->fpga_rst_ctrl);
  64        /* Set urgent bits with register */
  65        writel(0x0, &slcr_base->ddr_urgent_sel);
  66        /* Urgent write, ports S2/S3 */
  67        writel(0xC, &slcr_base->ddr_urgent);
  68#endif
  69#endif
  70        zynq_slcr_lock();
  71
  72        return 0;
  73}
  74
  75unsigned int zynq_get_silicon_version(void)
  76{
  77        return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
  78                                                >> ZYNQ_SILICON_VER_SHIFT;
  79}
  80
  81void reset_cpu(ulong addr)
  82{
  83        zynq_slcr_cpu_reset();
  84        while (1)
  85                ;
  86}
  87
  88#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  89void enable_caches(void)
  90{
  91        /* Enable D-cache. I-cache is already enabled in start.S */
  92        dcache_enable();
  93}
  94#endif
  95
  96static int __maybe_unused cpu_desc_id(void)
  97{
  98        u32 idcode;
  99        u8 i;
 100
 101        idcode = zynq_slcr_get_idcode();
 102        for (i = 0; zynq_fpga_descs[i].idcode; i++) {
 103                if (zynq_fpga_descs[i].idcode == idcode)
 104                        return i;
 105        }
 106
 107        return -ENODEV;
 108}
 109
 110#if defined(CONFIG_ARCH_EARLY_INIT_R)
 111int arch_early_init_r(void)
 112{
 113#if CONFIG_IS_ENABLED(FPGA)
 114        int cpu_id = cpu_desc_id();
 115
 116        if (cpu_id < 0)
 117                return 0;
 118
 119        fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
 120        fpga.name = zynq_fpga_descs[cpu_id].devicename;
 121        fpga_init();
 122        fpga_add(fpga_xilinx, &fpga);
 123#endif
 124        return 0;
 125}
 126#endif
 127
 128#ifdef CONFIG_DISPLAY_CPUINFO
 129int print_cpuinfo(void)
 130{
 131        u32 version;
 132        int cpu_id = cpu_desc_id();
 133
 134        if (cpu_id < 0)
 135                return 0;
 136
 137        version = zynq_get_silicon_version() << 1;
 138        if (version > (PCW_SILICON_VERSION_3 << 1))
 139                version += 1;
 140
 141        printf("CPU:   Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
 142        printf("Silicon: v%d.%d\n", version >> 1, version & 1);
 143        return 0;
 144}
 145#endif
 146