LXR uboot/arch/m68k/cpu/mcf547x_8x/cpu

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *
   4 * (C) Copyright 2000-2003
   5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6 *
   7 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
   8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   9 */
  10
  11#include <common.h>
  12#include <MCD_dma.h>
  13#include <cpu_func.h>
  14#include <init.h>
  15#include <asm/immap.h>
  16#include <asm/io.h>
  17
  18#if defined(CONFIG_CMD_NET)
  19#include <config.h>
  20#include <net.h>
  21#include <asm/fec.h>
  22#include <asm/fsl_mcdmafec.h>
  23#endif
  24
  25/*
  26 * Breath some life into the CPU...
  27 *
  28 * Set up the memory map,
  29 * initialize a bunch of registers,
  30 * initialize the UPM's
  31 */
  32void cpu_init_f(void)
  33{
  34        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  35        fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  36        xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
  37
  38        out_be32(&xlbarb->adrto, 0x2000);
  39        out_be32(&xlbarb->datto, 0x2500);
  40        out_be32(&xlbarb->busto, 0x3000);
  41
  42        out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
  43
  44        /* Master Priority Enable */
  45        out_be32(&xlbarb->prien, 0xff);
  46        out_be32(&xlbarb->pri, 0);
  47
  48#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  49        out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  50        out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  51        out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  52#endif
  53
  54#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  55        out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  56        out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  57        out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  58#endif
  59
  60#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  61        out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  62        out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  63        out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  64#endif
  65
  66#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  67        out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  68        out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  69        out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  70#endif
  71
  72#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  73        out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  74        out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  75        out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  76#endif
  77
  78#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
  79        out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  80        out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  81        out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  82#endif
  83
  84#ifdef CONFIG_SYS_I2C_FSL
  85        out_be16(&gpio->par_feci2cirq,
  86                GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
  87#endif
  88
  89        icache_enable();
  90}
  91
  92/*
  93 * initialize higher level parts of CPU like timers
  94 */
  95int cpu_init_r(void)
  96{
  97#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
  98        MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
  99                    MCD_RELOC_TASKS);
 100#endif
 101        return (0);
 102}
 103
 104void uart_port_conf(int port)
 105{
 106        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 107        u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
 108
 109        /* Setup Ports: */
 110        switch (port) {
 111        case 0:
 112                out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
 113                break;
 114        case 1:
 115                out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
 116                break;
 117        case 2:
 118                out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
 119                break;
 120        case 3:
 121                out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
 122                break;
 123        }
 124
 125        clrbits_8(pscsicr, 0x07);
 126}
 127
 128#if defined(CONFIG_CMD_NET)
 129int fecpin_setclear(fec_info_t *info, int setclear)
 130{
 131        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 132        u32 fec0_base;
 133
 134        if (fec_get_base_addr(0, &fec0_base))
 135                return -1;
 136
 137        if (setclear) {
 138                if (info->iobase == fec0_base)
 139                        setbits_be16(&gpio->par_feci2cirq, 0xf000);
 140                else
 141                        setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
 142        } else {
 143                if (info->iobase == fec0_base)
 144                        clrbits_be16(&gpio->par_feci2cirq, 0xf000);
 145                else
 146                        clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
 147        }
 148        return 0;
 149}
 150#endif
 151