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5
6#include <common.h>
7#include <env.h>
8#include <log.h>
9#include <time.h>
10#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
11#include <hwconfig.h>
12#endif
13#include <asm/fsl_serdes.h>
14#include <asm/immap_85xx.h>
15#include <asm/io.h>
16#include <asm/processor.h>
17#include <asm/fsl_law.h>
18#include <linux/delay.h>
19#include <linux/errno.h>
20#include "fsl_corenet_serdes.h"
21
22
23
24
25
26
27
28#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
29#ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
30#error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
31#endif
32#endif
33
34static u32 serdes_prtcl_map;
35
36#ifdef DEBUG
37static const char *serdes_prtcl_str[] = {
38 [NONE] = "NA",
39 [PCIE1] = "PCIE1",
40 [PCIE2] = "PCIE2",
41 [PCIE3] = "PCIE3",
42 [PCIE4] = "PCIE4",
43 [SATA1] = "SATA1",
44 [SATA2] = "SATA2",
45 [SRIO1] = "SRIO1",
46 [SRIO2] = "SRIO2",
47 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
48 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
49 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
50 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
51 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
52 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
53 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
54 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
55 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
56 [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
57 [XAUI_FM1] = "XAUI_FM1",
58 [XAUI_FM2] = "XAUI_FM2",
59 [AURORA] = "DEBUG",
60};
61#endif
62
63static const struct {
64 int idx;
65 unsigned int lpd;
66 int bank;
67} lanes[SRDS_MAX_LANES] = {
68 { 0, 152, FSL_SRDS_BANK_1 },
69 { 1, 153, FSL_SRDS_BANK_1 },
70 { 2, 154, FSL_SRDS_BANK_1 },
71 { 3, 155, FSL_SRDS_BANK_1 },
72 { 4, 156, FSL_SRDS_BANK_1 },
73 { 5, 157, FSL_SRDS_BANK_1 },
74 { 6, 158, FSL_SRDS_BANK_1 },
75 { 7, 159, FSL_SRDS_BANK_1 },
76 { 8, 160, FSL_SRDS_BANK_1 },
77 { 9, 161, FSL_SRDS_BANK_1 },
78 { 16, 162, FSL_SRDS_BANK_2 },
79 { 17, 163, FSL_SRDS_BANK_2 },
80 { 18, 164, FSL_SRDS_BANK_2 },
81 { 19, 165, FSL_SRDS_BANK_2 },
82#ifdef CONFIG_ARCH_P4080
83 { 20, 170, FSL_SRDS_BANK_3 },
84 { 21, 171, FSL_SRDS_BANK_3 },
85 { 22, 172, FSL_SRDS_BANK_3 },
86 { 23, 173, FSL_SRDS_BANK_3 },
87#else
88 { 20, 166, FSL_SRDS_BANK_3 },
89 { 21, 167, FSL_SRDS_BANK_3 },
90 { 22, 168, FSL_SRDS_BANK_3 },
91 { 23, 169, FSL_SRDS_BANK_3 },
92#endif
93#if SRDS_MAX_BANK > 3
94 { 24, 175, FSL_SRDS_BANK_4 },
95 { 25, 176, FSL_SRDS_BANK_4 },
96#endif
97};
98
99int serdes_get_lane_idx(int lane)
100{
101 return lanes[lane].idx;
102}
103
104int serdes_get_bank_by_lane(int lane)
105{
106 return lanes[lane].bank;
107}
108
109int serdes_lane_enabled(int lane)
110{
111 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
112 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
113
114 int bank = lanes[lane].bank;
115 int word = lanes[lane].lpd / 32;
116 int bit = lanes[lane].lpd % 32;
117
118 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
119 return 0;
120
121#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
122
123
124
125
126
127 if (bank > 0)
128 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
129#endif
130
131 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
132}
133
134int is_serdes_configured(enum srds_prtcl device)
135{
136 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
137
138
139 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
140 return 0;
141
142 if (!(serdes_prtcl_map & (1 << NONE)))
143 fsl_serdes_init();
144
145 return (1 << device) & serdes_prtcl_map;
146}
147
148static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
149{
150 int i;
151
152 for (i = 0; i < SRDS_MAX_LANES; i++) {
153 if (serdes_get_prtcl(prtcl, i) == device)
154 return i;
155 }
156
157 return -ENODEV;
158}
159
160
161
162
163
164
165
166
167int serdes_get_first_lane(enum srds_prtcl device)
168{
169 u32 prtcl;
170 const ccsr_gur_t *gur;
171
172 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
173
174
175 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
176 return -ENODEV;
177
178 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
179
180 return __serdes_get_first_lane(prtcl, device);
181}
182
183#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
184
185
186
187
188
189
190
191static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
192{
193 int lane;
194
195 lane = __serdes_get_first_lane(prtcl, device);
196 if (unlikely(lane < 0))
197 return lane;
198
199 return serdes_get_bank_by_lane(lane);
200}
201
202static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
203 int first)
204{
205 int lane;
206
207 for (lane = first; lane < SRDS_MAX_LANES; lane++) {
208 if (serdes_get_prtcl(prtcl, lane) != device)
209 break;
210 }
211
212 return lane - first;
213}
214
215static void __serdes_reset_rx(serdes_corenet_t *regs,
216 uint32_t prtcl,
217 enum srds_prtcl device)
218{
219 int lane, idx, first, last;
220
221 lane = __serdes_get_first_lane(prtcl, device);
222 if (unlikely(lane < 0))
223 return;
224 first = serdes_get_lane_idx(lane);
225 last = first + __serdes_get_lane_count(prtcl, device, lane);
226
227
228
229
230
231 for (idx = first; idx < last; idx++)
232 clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
233
234
235 udelay(1);
236
237
238
239
240
241 for (idx = first; idx < last; idx++)
242 setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
243}
244
245void serdes_reset_rx(enum srds_prtcl device)
246{
247 u32 prtcl;
248 const ccsr_gur_t *gur;
249 serdes_corenet_t *regs;
250
251 if (unlikely(device == NONE))
252 return;
253
254 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
255
256
257 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
258 return;
259
260 regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
261 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
262
263 __serdes_reset_rx(regs, prtcl, device);
264}
265#endif
266
267#ifndef CONFIG_SYS_DCSRBAR_PHYS
268#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000
269#define CONFIG_SYS_DCSRBAR 0x80000000
270#define __DCSR_NOT_DEFINED_BY_CONFIG
271#endif
272
273#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
274
275
276
277
278
279
280
281
282
283
284
285static void enable_bank(ccsr_gur_t *gur, int bank)
286{
287 u32 rcw5;
288 u32 temp_lpd_b = srds_lpd_b[bank];
289
290
291
292
293
294 if (temp_lpd_b == 0xF)
295 temp_lpd_b = 0xE;
296
297
298
299
300
301 rcw5 = in_be32(gur->rcwsr + 5);
302 if (bank == FSL_SRDS_BANK_2) {
303 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
304 rcw5 |= temp_lpd_b << 26;
305 } else if (bank == FSL_SRDS_BANK_3) {
306 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
307 rcw5 |= temp_lpd_b << 18;
308 } else {
309 printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
310 return;
311 }
312
313
314
315
316 {
317#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
318 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
319 int law_index;
320 if (law.index == -1)
321 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
322 LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
323 else
324 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
325 LAW_TRGT_IF_DCSR);
326#endif
327 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
328 out_be32(p, rcw5);
329#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
330 if (law.index == -1)
331 disable_law(law_index);
332 else
333 set_law(law.index, law.addr, law.size, law.trgt_id);
334#endif
335 }
336}
337
338
339
340
341
342
343
344
345
346static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
347 u32 devdisr, u32 devdisr2, int cfg)
348{
349 int srds_ratio_b2;
350 int rfck_sel;
351
352
353
354
355
356
357
358
359
360 clrbits_be32(&gur->devdisr, devdisr);
361 clrbits_be32(&gur->devdisr2, devdisr2);
362
363
364
365
366
367
368
369 switch (cfg) {
370 case 0x19:
371
372
373
374
375 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
376 SRDS_PLLCR1_PLL_BWSEL);
377 break;
378
379 case 0x0f:
380 case 0x10:
381
382
383
384
385
386
387
388 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
389
390
391 switch (srds_ratio_b2) {
392 case 1:
393 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
394 break;
395 case 2:
396 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
397 break;
398 default:
399 printf("SERDES: bad SRDS_RATIO_B2 %d\n",
400 srds_ratio_b2);
401 return;
402 }
403
404 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
405 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
406
407 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
408 SRDS_PLLCR0_FRATE_SEL_MASK,
409 SRDS_PLLCR0_FRATE_SEL_6_25);
410 break;
411 }
412
413 enable_bank(gur, FSL_SRDS_BANK_3);
414}
415#endif
416
417#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
418
419
420
421
422static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
423{
424 enum srds_prtcl device;
425
426 switch (cfg) {
427 case 0x13:
428 case 0x16:
429
430
431
432
433 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
434 SRDS_PLLCR1_PLL_BWSEL);
435 break;
436 case 0x19:
437
438
439
440
441 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
442 SRDS_PLLCR1_PLL_BWSEL);
443 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
444 SRDS_PLLCR1_PLL_BWSEL);
445 break;
446 }
447
448
449
450
451
452 for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
453 if (is_serdes_configured(device)) {
454 int bank = serdes_get_bank_by_device(cfg, device);
455
456 clrbits_be32(®s->bank[bank].pllcr1,
457 SRDS_PLLCR1_PLL_BWSEL);
458 }
459 }
460}
461#endif
462
463
464
465
466static void wait_for_rstdone(unsigned int bank)
467{
468 serdes_corenet_t *srds_regs =
469 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
470 unsigned long long end_tick;
471 u32 rstctl;
472
473
474 end_tick = usec2ticks(1000000) + get_ticks();
475 do {
476 rstctl = in_be32(&srds_regs->bank[bank].rstctl);
477 if (rstctl & SRDS_RSTCTL_RSTDONE)
478 break;
479 } while (end_tick > get_ticks());
480
481 if (!(rstctl & SRDS_RSTCTL_RSTDONE))
482 printf("SERDES: timeout resetting bank %u\n", bank + 1);
483}
484
485
486static void __soc_serdes_init(void)
487{
488
489};
490void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
491
492void fsl_serdes_init(void)
493{
494 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
495 int cfg;
496 serdes_corenet_t *srds_regs;
497#ifdef CONFIG_ARCH_P5040
498 serdes_corenet_t *srds2_regs;
499#endif
500 int lane, bank, idx;
501 int have_bank[SRDS_MAX_BANK] = {};
502#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
503 u32 serdes8_devdisr = 0;
504 u32 serdes8_devdisr2 = 0;
505 char srds_lpd_opt[16];
506 const char *srds_lpd_arg;
507 size_t arglen;
508#endif
509#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
510 int need_serdes_a001;
511#endif
512#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
513 char buffer[HWCONFIG_BUFFER_SIZE];
514 char *buf = NULL;
515
516
517
518
519
520 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
521 buf = buffer;
522#endif
523 if (serdes_prtcl_map & (1 << NONE))
524 return;
525
526
527 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
528 return;
529
530 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
531 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
532 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
533
534 if (!is_serdes_prtcl_valid(cfg)) {
535 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
536 return;
537 }
538
539#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
540
541
542
543
544
545#define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
546 if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) {
547 printf("Warning: SERDES8 requires banks two and "
548 "three to be disabled in the RCW\n");
549 }
550
551
552
553
554
555
556 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
557 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
558 srds_lpd_arg =
559 hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
560 if (srds_lpd_arg)
561 srds_lpd_b[bank] =
562 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
563 }
564
565 if ((cfg == 0xf) || (cfg == 0x10)) {
566
567
568
569
570 srds_lpd_b[FSL_SRDS_BANK_3] = 0xF;
571 }
572#endif
573
574
575 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
576 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
577 if (serdes_lane_enabled(lane)) {
578 have_bank[serdes_get_bank_by_lane(lane)] = 1;
579 serdes_prtcl_map |= (1 << lane_prtcl);
580 }
581 }
582
583#ifdef CONFIG_ARCH_P5040
584
585
586
587
588
589
590
591
592 switch (cfg) {
593 case 0x0:
594 case 0x1:
595 case 0x2:
596 case 0x3:
597 case 0x4:
598 case 0x5:
599 case 0x6:
600 case 0x7:
601 serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
602 break;
603 default:
604 srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
605
606
607 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
608 }
609#endif
610
611 soc_serdes_init();
612
613
614 serdes_prtcl_map |= (1 << NONE);
615
616#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
617
618
619
620
621 if (have_bank[FSL_SRDS_BANK_2])
622 have_bank[FSL_SRDS_BANK_3] = 1;
623#endif
624
625#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
626
627
628
629
630
631
632
633 need_serdes_a001 =
634 !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3];
635#endif
636
637
638 for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
639 if (!have_bank[bank]) {
640 printf("SERDES: bank %d disabled\n", bank + 1);
641#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
642
643
644
645
646
647 if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2))
648 setbits_be32(&srds_regs->bank[bank].rstctl,
649 SRDS_RSTCTL_SDPD);
650#else
651 setbits_be32(&srds_regs->bank[bank].rstctl,
652 SRDS_RSTCTL_SDPD);
653#endif
654 }
655 }
656
657#ifdef CONFIG_SYS_FSL_ERRATUM_A004699
658
659
660
661
662
663
664
665
666
667
668 for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
669
670 unsigned int lane;
671
672 for (lane = 0; lane < SRDS_MAX_LANES; lane++)
673 if (lanes[lane].bank == bank)
674 break;
675 idx = lanes[lane].idx;
676
677
678
679
680
681 if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
682
683 setbits_be32(&srds_regs->bank[bank].pllcr0,
684 SRDS_PLLCR0_PVCOCNT_EN);
685 }
686 }
687#endif
688
689#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
690 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
691 enum srds_prtcl lane_prtcl;
692
693 idx = serdes_get_lane_idx(lane);
694 lane_prtcl = serdes_get_prtcl(cfg, lane);
695
696#ifdef DEBUG
697 switch (lane) {
698 case 0:
699 puts("Bank1: ");
700 break;
701 case 10:
702 puts("\nBank2: ");
703 break;
704 case 14:
705 puts("\nBank3: ");
706 break;
707 default:
708 break;
709 }
710
711 printf("%s ", serdes_prtcl_str[lane_prtcl]);
712#endif
713
714#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
715
716
717
718
719
720
721
722
723
724 switch (lane_prtcl) {
725 case SGMII_FM1_DTSEC1:
726 case SGMII_FM1_DTSEC2:
727 case SGMII_FM1_DTSEC3:
728 case SGMII_FM1_DTSEC4:
729 case SGMII_FM2_DTSEC1:
730 case SGMII_FM2_DTSEC2:
731 case SGMII_FM2_DTSEC3:
732 case SGMII_FM2_DTSEC4:
733 case SGMII_FM2_DTSEC5:
734 case XAUI_FM1:
735 case XAUI_FM2:
736 case SRIO1:
737 case SRIO2:
738 case AURORA:
739 out_be32(&srds_regs->lane[idx].ttlcr0,
740 SRDS_TTLCR0_FLT_SEL_KFR_26 |
741 SRDS_TTLCR0_FLT_SEL_KPH_28 |
742 SRDS_TTLCR0_FLT_SEL_750PPM |
743 SRDS_TTLCR0_FREQOVD_EN);
744 break;
745 default:
746 break;
747 }
748#endif
749
750#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
751 switch (lane_prtcl) {
752 case PCIE1:
753 case PCIE2:
754 case PCIE3:
755 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
756 (lane_prtcl - PCIE1);
757 break;
758 case SRIO1:
759 case SRIO2:
760 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
761 (lane_prtcl - SRIO1);
762 break;
763 case SGMII_FM1_DTSEC1:
764 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
765 FSL_CORENET_DEVDISR2_DTSEC1_1;
766 break;
767 case SGMII_FM1_DTSEC2:
768 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
769 FSL_CORENET_DEVDISR2_DTSEC1_2;
770 break;
771 case SGMII_FM1_DTSEC3:
772 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
773 FSL_CORENET_DEVDISR2_DTSEC1_3;
774 break;
775 case SGMII_FM1_DTSEC4:
776 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
777 FSL_CORENET_DEVDISR2_DTSEC1_4;
778 break;
779 case SGMII_FM2_DTSEC1:
780 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
781 FSL_CORENET_DEVDISR2_DTSEC2_1;
782 break;
783 case SGMII_FM2_DTSEC2:
784 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
785 FSL_CORENET_DEVDISR2_DTSEC2_2;
786 break;
787 case SGMII_FM2_DTSEC3:
788 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
789 FSL_CORENET_DEVDISR2_DTSEC2_3;
790 break;
791 case SGMII_FM2_DTSEC4:
792 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
793 FSL_CORENET_DEVDISR2_DTSEC2_4;
794 break;
795 case SGMII_FM2_DTSEC5:
796 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
797 FSL_CORENET_DEVDISR2_DTSEC2_5;
798 break;
799 case XAUI_FM1:
800 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
801 FSL_CORENET_DEVDISR2_10GEC1;
802 break;
803 case XAUI_FM2:
804 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
805 FSL_CORENET_DEVDISR2_10GEC2;
806 break;
807 case AURORA:
808 break;
809 default:
810 break;
811 }
812
813#endif
814 }
815#endif
816
817#ifdef DEBUG
818 puts("\n");
819#endif
820
821#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
822 p4080_erratum_serdes_a005(srds_regs, cfg);
823#endif
824
825 for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
826 bank = idx;
827
828#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
829
830
831
832
833
834
835 if (idx == 1)
836 bank = FSL_SRDS_BANK_3;
837 else if (idx == 2)
838 bank = FSL_SRDS_BANK_2;
839#endif
840
841
842 if (!have_bank[bank])
843 continue;
844
845#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
846 if (idx == 1) {
847
848
849
850
851
852
853 p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
854 serdes8_devdisr2, cfg);
855 } else if (idx == 2) {
856
857 enable_bank(gur, FSL_SRDS_BANK_2);
858 }
859#endif
860
861 wait_for_rstdone(bank);
862 }
863
864#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
865 if (need_serdes_a001) {
866
867 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl,
868 SRDS_RSTCTL_SDPD);
869 }
870#endif
871}
872
873const char *serdes_clock_to_string(u32 clock)
874{
875 switch (clock) {
876 case SRDS_PLLCR0_RFCK_SEL_100:
877 return "100";
878 case SRDS_PLLCR0_RFCK_SEL_125:
879 return "125";
880 case SRDS_PLLCR0_RFCK_SEL_156_25:
881 return "156.25";
882 case SRDS_PLLCR0_RFCK_SEL_161_13:
883 return "161.1328123";
884 default:
885 return "150";
886 }
887}
888
889