LXR uboot/arch/powerpc/cpu/mpc86xx/interrupts.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2000-2002
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 *
   6 * (C) Copyright 2002 (440 port)
   7 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
   8 *
   9 * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
  10 * Xianghua Xiao (X.Xiao@motorola.com)
  11 *
  12 * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
  13 * Jeff Brown
  14 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  15 */
  16
  17#include <common.h>
  18#include <irq_func.h>
  19#include <log.h>
  20#include <mpc86xx.h>
  21#include <command.h>
  22#include <time.h>
  23#include <asm/processor.h>
  24#ifdef CONFIG_POST
  25#include <post.h>
  26#endif
  27#include <asm/ptrace.h>
  28
  29void interrupt_init_cpu(unsigned *decrementer_count)
  30{
  31        volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  32        volatile ccsr_pic_t *pic = &immr->im_pic;
  33
  34#ifdef CONFIG_POST
  35        /*
  36         * The POST word is stored in the PIC's TFRR register which gets
  37         * cleared when the PIC is reset.  Save it off so we can restore it
  38         * later.
  39         */
  40        ulong post_word = post_word_load();
  41#endif
  42
  43        pic->gcr = MPC86xx_PICGCR_RST;
  44        while (pic->gcr & MPC86xx_PICGCR_RST)
  45                ;
  46        pic->gcr = MPC86xx_PICGCR_MODE;
  47
  48        *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
  49        debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n",
  50              (get_tbclk() / 1000000),
  51              *decrementer_count);
  52
  53#ifdef CONFIG_INTERRUPTS
  54
  55        pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
  56        debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
  57
  58        pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
  59        debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
  60
  61        pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
  62        debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
  63
  64#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
  65        pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
  66        debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
  67#endif
  68#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
  69        pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
  70        debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
  71#endif
  72
  73        pic->ctpr = 0;  /* 40080 clear current task priority register */
  74#endif
  75
  76#ifdef CONFIG_POST
  77        post_word_store(post_word);
  78#endif
  79}
  80
  81/*
  82 * timer_interrupt - gets called when the decrementer overflows,
  83 * with interrupts disabled.
  84 * Trivial implementation - no need to be really accurate.
  85 */
  86void timer_interrupt_cpu(struct pt_regs *regs)
  87{
  88        /* nothing to do here */
  89}
  90
  91/*
  92 * Install and free a interrupt handler. Not implemented yet.
  93 */
  94void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
  95{
  96}
  97
  98void irq_free_handler(int vec)
  99{
 100}
 101
 102/*
 103 * irqinfo - print information about PCI devices,not implemented.
 104 */
 105int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 106{
 107        return 0;
 108}
 109
 110/*
 111 * Handle external interrupts
 112 */
 113void external_interrupt(struct pt_regs *regs)
 114{
 115        puts("external_interrupt(oops!)\n");
 116}
 117