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6#ifndef _ASM_MPC85xx_CONFIG_H_
7#define _ASM_MPC85xx_CONFIG_H_
8
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12
13
14
15#define CONFIG_PPC_SPINTABLE_COMPATIBLE
16
17#include <fsl_ddrc_version.h>
18
19
20#define CONFIG_SYS_FSL_IFC_BE
21#define CONFIG_SYS_FSL_SFP_BE
22#define CONFIG_SYS_FSL_SEC_MON_BE
23
24#if defined(CONFIG_ARCH_MPC8548)
25#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
26#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
27#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
28#define CONFIG_SYS_FSL_RMU
29#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
30
31#elif defined(CONFIG_ARCH_MPC8568)
32#define QE_MURAM_SIZE 0x10000UL
33#define MAX_QE_RISC 2
34#define QE_NUM_OF_SNUM 28
35#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
36#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
37#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
38#define CONFIG_SYS_FSL_RMU
39#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
40
41#elif defined(CONFIG_ARCH_MPC8569)
42#define QE_MURAM_SIZE 0x20000UL
43#define MAX_QE_RISC 4
44#define QE_NUM_OF_SNUM 46
45#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
46#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
47#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
48#define CONFIG_SYS_FSL_RMU
49#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
50
51#elif defined(CONFIG_ARCH_P1010)
52#define CONFIG_FSL_SDHC_V2_3
53#define CONFIG_TSECV2
54#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
55#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
56#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
57#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
58#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
59#define CONFIG_ESDHC_HC_BLK_ADDR
60
61
62#elif defined(CONFIG_ARCH_P1011)
63#define CONFIG_TSECV2
64#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
65
66#elif defined(CONFIG_ARCH_P1020)
67#define CONFIG_TSECV2
68#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
69#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
70#endif
71
72#elif defined(CONFIG_ARCH_P1021)
73#define CONFIG_TSECV2
74#define QE_MURAM_SIZE 0x6000UL
75#define MAX_QE_RISC 1
76#define QE_NUM_OF_SNUM 28
77#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
78
79#elif defined(CONFIG_ARCH_P1022)
80#define CONFIG_TSECV2
81#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
82
83#elif defined(CONFIG_ARCH_P1023)
84#define CONFIG_SYS_NUM_FMAN 1
85#define CONFIG_SYS_NUM_FM1_DTSEC 2
86#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
87#define CONFIG_SYS_QMAN_NUM_PORTALS 3
88#define CONFIG_SYS_BMAN_NUM_PORTALS 3
89#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
90#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
91
92
93#elif defined(CONFIG_ARCH_P1024)
94#define CONFIG_TSECV2
95#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
96
97
98#elif defined(CONFIG_ARCH_P1025)
99#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
100#define CONFIG_TSECV2
101#define QE_MURAM_SIZE 0x6000UL
102#define MAX_QE_RISC 1
103#define QE_NUM_OF_SNUM 28
104
105#elif defined(CONFIG_ARCH_P2020)
106#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
107#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
108#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
109#define CONFIG_SYS_FSL_RMU
110#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
111#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
112
113#elif defined(CONFIG_ARCH_P2041)
114#define CONFIG_FSL_CORENET
115#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
116#define CONFIG_SYS_NUM_FMAN 1
117#define CONFIG_SYS_NUM_FM1_DTSEC 5
118#define CONFIG_SYS_NUM_FM1_10GEC 1
119#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
120#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
121#endif
122#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
123#define CONFIG_SYS_FSL_TBCLK_DIV 32
124#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
125#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
126#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
127#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
128#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
129#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
130#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
131#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
132
133#elif defined(CONFIG_ARCH_P3041)
134#define CONFIG_FSL_CORENET
135#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
136#define CONFIG_SYS_NUM_FMAN 1
137#define CONFIG_SYS_NUM_FM1_DTSEC 5
138#define CONFIG_SYS_NUM_FM1_10GEC 1
139#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
140#define CONFIG_SYS_FSL_TBCLK_DIV 32
141#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
142#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
143#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
144#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
145#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
146#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
147#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
148#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
149#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
150
151#elif defined(CONFIG_ARCH_P4080)
152#define CONFIG_FSL_CORENET
153#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
154#define CONFIG_SYS_NUM_FMAN 2
155#define CONFIG_SYS_NUM_FM1_DTSEC 4
156#define CONFIG_SYS_NUM_FM2_DTSEC 4
157#define CONFIG_SYS_NUM_FM1_10GEC 1
158#define CONFIG_SYS_NUM_FM2_10GEC 1
159#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
160#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
161#define CONFIG_SYS_FSL_TBCLK_DIV 16
162#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
163#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
164#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
165#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
166#define CONFIG_SYS_FSL_RMU
167#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
168#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
169
170#elif defined(CONFIG_ARCH_P5020)
171#define CONFIG_FSL_CORENET
172#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
173#define CONFIG_SYS_NUM_FMAN 1
174#define CONFIG_SYS_NUM_FM1_DTSEC 5
175#define CONFIG_SYS_NUM_FM1_10GEC 1
176#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
177#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
178#define CONFIG_SYS_FSL_TBCLK_DIV 32
179#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
180#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
181#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
182#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
183#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
184#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
185#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
186#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
187
188#elif defined(CONFIG_ARCH_P5040)
189#define CONFIG_FSL_CORENET
190#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
191#define CONFIG_SYS_NUM_FMAN 2
192#define CONFIG_SYS_NUM_FM1_DTSEC 5
193#define CONFIG_SYS_NUM_FM1_10GEC 1
194#define CONFIG_SYS_NUM_FM2_DTSEC 5
195#define CONFIG_SYS_NUM_FM2_10GEC 1
196#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
197#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
198#define CONFIG_SYS_FSL_TBCLK_DIV 16
199#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
200#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
201#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
202#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
203#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
204
205#elif defined(CONFIG_ARCH_BSC9131)
206#define CONFIG_FSL_SDHC_V2_3
207#define CONFIG_TSECV2
208#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
209#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
210#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
211#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
212#define CONFIG_NAND_FSL_IFC
213#define CONFIG_ESDHC_HC_BLK_ADDR
214
215#elif defined(CONFIG_ARCH_BSC9132)
216#define CONFIG_FSL_SDHC_V2_3
217#define CONFIG_TSECV2
218#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
219#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
220#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
221#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
222#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
223#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
224#define CONFIG_NAND_FSL_IFC
225#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
226#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
227#define CONFIG_ESDHC_HC_BLK_ADDR
228
229#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
230#define CONFIG_FSL_CORENET
231#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
232#define CONFIG_SYS_FSL_QMAN_V3
233#ifdef CONFIG_ARCH_T4240
234#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
235#define CONFIG_SYS_NUM_FM1_DTSEC 8
236#define CONFIG_SYS_NUM_FM1_10GEC 2
237#define CONFIG_SYS_NUM_FM2_DTSEC 8
238#define CONFIG_SYS_NUM_FM2_10GEC 2
239#else
240#define CONFIG_SYS_NUM_FM1_DTSEC 6
241#define CONFIG_SYS_NUM_FM1_10GEC 1
242#define CONFIG_SYS_NUM_FM2_DTSEC 8
243#define CONFIG_SYS_NUM_FM2_10GEC 1
244#if defined(CONFIG_ARCH_T4160)
245#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
246#endif
247#endif
248#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
249#define CONFIG_SYS_FSL_SRDS_1
250#define CONFIG_SYS_FSL_SRDS_2
251#define CONFIG_SYS_FSL_SRDS_3
252#define CONFIG_SYS_FSL_SRDS_4
253#define CONFIG_SYS_NUM_FMAN 2
254#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
255#define CONFIG_SYS_PME_CLK 0
256#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
257#define CONFIG_SYS_FMAN_V3
258#define CONFIG_SYS_FM1_CLK 3
259#define CONFIG_SYS_FM2_CLK 3
260#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
261#define CONFIG_SYS_FSL_TBCLK_DIV 16
262#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
263#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
264#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
265#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
266#define CONFIG_SYS_FSL_SRIO_LIODN
267#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
268#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
269#define CONFIG_SYS_FSL_SFP_VER_3_0
270#define CONFIG_SYS_FSL_PCI_VER_3_X
271
272#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
273#define CONFIG_FSL_CORENET
274#define CONFIG_SYS_FSL_QMAN_V3
275#define CONFIG_HETROGENOUS_CLUSTERS
276#define CONFIG_PPC_CLUSTER_START 0
277#define CONFIG_DSP_CLUSTER_START 1
278#define CONFIG_SYS_FSL_SRDS_1
279#define CONFIG_SYS_FSL_SRDS_2
280#define CONFIG_SYS_MAPLE
281#define CONFIG_SYS_CPRI
282#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
283#define CONFIG_SYS_NUM_FMAN 1
284#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
285#define CONFIG_SYS_FM1_CLK 0
286#define CONFIG_SYS_CPRI_CLK 3
287#define CONFIG_SYS_ULB_CLK 4
288#define CONFIG_SYS_ETVPE_CLK 1
289#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
290#define CONFIG_SYS_FMAN_V3
291#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
292#define CONFIG_SYS_FSL_TBCLK_DIV 16
293#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
294#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
295#define CONFIG_SYS_FSL_SFP_VER_3_0
296
297#ifdef CONFIG_ARCH_B4860
298#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
299#define CONFIG_MAX_DSP_CPUS 12
300#define CONFIG_NUM_DSP_CPUS 6
301#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
302#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
303#define CONFIG_SYS_NUM_FM1_DTSEC 6
304#define CONFIG_SYS_NUM_FM1_10GEC 2
305#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
306#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
307#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
308#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
309#define CONFIG_SYS_FSL_SRIO_LIODN
310#else
311#define CONFIG_MAX_DSP_CPUS 2
312#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
313#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
314#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
315#define CONFIG_SYS_NUM_FM1_DTSEC 4
316#define CONFIG_SYS_NUM_FM1_10GEC 0
317#endif
318
319#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
320#define CONFIG_E5500
321#define CONFIG_FSL_CORENET
322#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
323#define CONFIG_SYS_FSL_QMAN_V3
324#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
325#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
326#define CONFIG_SYS_FSL_SRDS_1
327#define CONFIG_SYS_NUM_FMAN 1
328#define CONFIG_SYS_NUM_FM1_DTSEC 5
329#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
330#define CONFIG_PME_PLAT_CLK_DIV 2
331#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
332#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
333#define CONFIG_SYS_FMAN_V3
334#define CONFIG_FM_PLAT_CLK_DIV 1
335#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
336#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
337#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
338#define CONFIG_SYS_FSL_TBCLK_DIV 16
339#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
340#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
341#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
342#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
343#define QE_MURAM_SIZE 0x6000UL
344#define MAX_QE_RISC 1
345#define QE_NUM_OF_SNUM 28
346#define CONFIG_SYS_FSL_SFP_VER_3_0
347
348#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
349#define CONFIG_E5500
350#define CONFIG_FSL_CORENET
351#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
352#define CONFIG_SYS_FSL_QMAN_V3
353#define CONFIG_SYS_FMAN_V3
354#define CONFIG_SYS_FSL_NUM_CC_PLL 2
355#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
356#define CONFIG_SYS_FSL_SRDS_1
357#define CONFIG_SYS_NUM_FMAN 1
358#define CONFIG_SYS_NUM_FM1_DTSEC 4
359#define CONFIG_SYS_NUM_FM1_10GEC 1
360#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
361#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
362#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
363#define CONFIG_SYS_FM1_CLK 0
364#define CONFIG_QBMAN_CLK_DIV 1
365#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
366#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
367#define CONFIG_SYS_FSL_TBCLK_DIV 16
368#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
369#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
370#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
371#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
372#define QE_MURAM_SIZE 0x6000UL
373#define MAX_QE_RISC 1
374#define QE_NUM_OF_SNUM 28
375#define CONFIG_SYS_FSL_SFP_VER_3_0
376
377#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
378#define CONFIG_FSL_CORENET
379#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
380#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
381#define CONFIG_SYS_FSL_QMAN_V3
382#define CONFIG_SYS_NUM_FMAN 1
383#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
384#define CONFIG_SYS_FSL_SRDS_1
385#define CONFIG_SYS_FSL_PCI_VER_3_X
386#if defined(CONFIG_ARCH_T2080)
387#define CONFIG_SYS_NUM_FM1_DTSEC 8
388#define CONFIG_SYS_NUM_FM1_10GEC 4
389#define CONFIG_SYS_FSL_SRDS_2
390#define CONFIG_SYS_FSL_SRIO_LIODN
391#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
392#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
393#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
394#elif defined(CONFIG_ARCH_T2081)
395#define CONFIG_SYS_NUM_FM1_DTSEC 6
396#define CONFIG_SYS_NUM_FM1_10GEC 2
397#endif
398#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
399#define CONFIG_PME_PLAT_CLK_DIV 1
400#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
401#define CONFIG_SYS_FM1_CLK 0
402#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
403#define CONFIG_SYS_FMAN_V3
404#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
405#define CONFIG_SYS_FSL_TBCLK_DIV 16
406#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
407#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
408#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
409#define CONFIG_SYS_FSL_SFP_VER_3_0
410#define CONFIG_SYS_FSL_ISBC_VER 2
411#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
412#define CONFIG_SYS_FSL_SFP_VER_3_0
413
414
415#elif defined(CONFIG_ARCH_C29X)
416#define CONFIG_FSL_SDHC_V2_3
417#define CONFIG_TSECV2_1
418#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
419#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
420#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
421
422#endif
423
424#if !defined(CONFIG_ARCH_C29X)
425#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
426#endif
427
428#endif
429