LXR uboot/arch/x86/cpu/coreboot/coreboot.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (c) 2011 The Chromium OS Authors.
   4 * (C) Copyright 2008
   5 * Graeme Russ, graeme.russ@gmail.com.
   6 */
   7
   8#include <common.h>
   9#include <cpu_func.h>
  10#include <fdtdec.h>
  11#include <init.h>
  12#include <usb.h>
  13#include <asm/io.h>
  14#include <asm/msr.h>
  15#include <asm/mtrr.h>
  16#include <asm/arch/sysinfo.h>
  17#include <asm/arch/timestamp.h>
  18
  19DECLARE_GLOBAL_DATA_PTR;
  20
  21int arch_cpu_init(void)
  22{
  23        int ret = get_coreboot_info(&lib_sysinfo);
  24        if (ret != 0) {
  25                printf("Failed to parse coreboot tables.\n");
  26                return ret;
  27        }
  28
  29        timestamp_init();
  30
  31        return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
  32                 x86_cpu_init_f();
  33}
  34
  35int checkcpu(void)
  36{
  37        return 0;
  38}
  39
  40int print_cpuinfo(void)
  41{
  42        return default_print_cpuinfo();
  43}
  44
  45static void board_final_init(void)
  46{
  47        /*
  48         * Un-cache the ROM so the kernel has one
  49         * more MTRR available.
  50         *
  51         * Coreboot should have assigned this to the
  52         * top available variable MTRR.
  53         */
  54        u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
  55        u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
  56
  57        /* Make sure this MTRR is the correct Write-Protected type */
  58        if (top_type == MTRR_TYPE_WRPROT) {
  59                struct mtrr_state state;
  60
  61                mtrr_open(&state, true);
  62                wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
  63                wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
  64                mtrr_close(&state, true);
  65        }
  66
  67        if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
  68                /*
  69                 * Issue SMI to coreboot to lock down ME and registers
  70                 * when allowed via device tree
  71                 */
  72                printf("Finalizing coreboot\n");
  73                outb(0xcb, 0xb2);
  74        }
  75}
  76
  77int last_stage_init(void)
  78{
  79        /* start usb so that usb keyboard can be used as input device */
  80        if (CONFIG_IS_ENABLED(USB_KEYBOARD))
  81                usb_init();
  82
  83        board_final_init();
  84
  85        return 0;
  86}
  87