LXR uboot/arch/x86/include/asm/arch-broadwell/pei

   1/* SPDX-License-Identifier: BSD-3-Clause */
   2/*
   3 * From Coreboot soc/intel/broadwell/include/soc/pei_data.h
   4 *
   5 * Copyright (C) 2014 Google Inc.
   6 */
   7
   8#ifndef ASM_ARCH_PEI_DATA_H
   9#define ASM_ARCH_PEI_DATA_H
  10
  11#include <linux/linkage.h>
  12
  13#define PEI_VERSION 22
  14
  15typedef void asmlinkage (*tx_byte_func)(unsigned char byte);
  16
  17enum board_type {
  18        BOARD_TYPE_CRB_MOBILE = 0,      /* CRB Mobile */
  19        BOARD_TYPE_CRB_DESKTOP,         /* CRB Desktop */
  20        BOARD_TYPE_USER1,               /* SV mobile */
  21        BOARD_TYPE_USER2,               /* SV desktop */
  22        BOARD_TYPE_USER3,               /* SV server */
  23        BOARD_TYPE_ULT,                 /* ULT */
  24        BOARD_TYPE_CRB_EMBDEDDED,       /* CRB Embedded */
  25        BOARD_TYPE_UNKNOWN,
  26};
  27
  28#define MAX_USB2_PORTS 14
  29#define MAX_USB3_PORTS 6
  30#define USB_OC_PIN_SKIP 8
  31
  32enum usb2_port_location {
  33        USB_PORT_BACK_PANEL = 0,
  34        USB_PORT_FRONT_PANEL,
  35        USB_PORT_DOCK,
  36        USB_PORT_MINI_PCIE,
  37        USB_PORT_FLEX,
  38        USB_PORT_INTERNAL,
  39        USB_PORT_SKIP,
  40        USB_PORT_NGFF_DEVICE_DOWN,
  41};
  42
  43struct usb2_port_setting {
  44        /*
  45         * Usb Port Length:
  46         * [16:4] = length in inches in octal format
  47         * [3:0]  = decimal point
  48         */
  49        uint16_t length;
  50        uint8_t enable;
  51        uint8_t oc_pin;
  52        uint8_t location;
  53} __packed;
  54
  55struct usb3_port_setting {
  56        uint8_t enable;
  57        uint8_t oc_pin;
  58        /*
  59         * Set to 0 if trace length is > 5 inches
  60         * Set to 1 if trace length is <= 5 inches
  61         */
  62        uint8_t fixed_eq;
  63} __packed;
  64
  65
  66struct pei_data {
  67        uint32_t pei_version;
  68
  69        enum board_type board_type;
  70        int boot_mode;
  71        int ec_present;
  72        int usbdebug;
  73
  74        /* Base addresses */
  75        uint32_t pciexbar;
  76        uint16_t smbusbar;
  77        uint32_t xhcibar;
  78        uint32_t ehcibar;
  79        uint32_t gttbar;
  80        uint32_t rcba;
  81        uint32_t pmbase;
  82        uint32_t gpiobase;
  83        uint32_t temp_mmio_base;
  84        uint32_t tseg_size;
  85
  86        /*
  87         * 0 = leave channel enabled
  88         * 1 = disable dimm 0 on channel
  89         * 2 = disable dimm 1 on channel
  90         * 3 = disable dimm 0+1 on channel
  91         */
  92        int dimm_channel0_disabled;
  93        int dimm_channel1_disabled;
  94        /* Set to 0 for memory down */
  95        uint8_t spd_addresses[4];
  96        /* Enable 2x Refresh Mode */
  97        int ddr_refresh_2x;
  98        /* DQ pins are interleaved on board */
  99        int dq_pins_interleaved;
 100        /* Limit DDR3 frequency */
 101        int max_ddr3_freq;
 102        /* Disable self refresh */
 103        int disable_self_refresh;
 104        /* Disable cmd power/CKEPD */
 105        int disable_cmd_pwr;
 106
 107        /* USB port configuration */
 108        struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
 109        struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
 110
 111        /*
 112         * USB3 board specific PHY tuning
 113         */
 114
 115        /* Valid range: 0x69 - 0x80 */
 116        uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
 117        /* Valid range: 0x80 - 0x9c */
 118        uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
 119        /* Valid range: 0x39 - 0x80 */
 120        uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
 121        /* Valid range: 0x3d - 0x4a */
 122        uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
 123
 124        /* Console output function */
 125        tx_byte_func tx_byte;
 126
 127        /*
 128         * DIMM SPD data for memory down configurations
 129         * [CHANNEL][SLOT][SPD]
 130         */
 131        uint8_t spd_data[2][2][512];
 132
 133        /*
 134         * LPDDR3 DQ byte map
 135         * [CHANNEL][ITERATION][2]
 136         *
 137         * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
 138         * DQByteMap[0] - ClkDQByteMap:
 139         * - If clock is per rank, program to [0xFF, 0xFF]
 140         * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
 141         * - If clock is shared by 2 ranks but does not go to all bytes,
 142         *   Entry[i] defines which DQ bytes Group i services
 143         * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
 144         * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
 145         * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
 146         *                For DDR, DQByteMap[3:1] = [0xFF, 0]
 147         * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
 148         *                since we have 1 CTL / rank
 149         * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
 150         *                since we have 1 CA Vref
 151         */
 152        uint8_t dq_map[2][6][2];
 153
 154        /*
 155         * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
 156         * [CHANNEL][MAX_BYTES]
 157         */
 158        uint8_t dqs_map[2][8];
 159
 160        /* Data read from flash and passed into MRC */
 161        const void *saved_data;
 162        int saved_data_size;
 163
 164        /* Disable use of saved data (can be set by mainboard) */
 165        int disable_saved_data;
 166
 167        /* Data from MRC that should be saved to flash */
 168        void *data_to_save;
 169        int data_to_save_size;
 170        struct pei_memory_info meminfo;
 171} __packed;
 172
 173void mainboard_fill_pei_data(struct pei_data *pei_data);
 174void broadwell_fill_pei_data(struct pei_data *pei_data);
 175
 176#endif
 177