LXR uboot/board/cssi/MCR3000/MCR3000.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2010-2017 CS Systemes d'Information
   4 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
   5 * Christophe Leroy <christophe.leroy@c-s.fr>
   6 *
   7 * Board specific routines for the MCR3000 board
   8 */
   9
  10#include <common.h>
  11#include <env.h>
  12#include <hwconfig.h>
  13#include <init.h>
  14#include <mpc8xx.h>
  15#include <fdt_support.h>
  16#include <serial.h>
  17#include <asm/io.h>
  18#include <dm/uclass.h>
  19#include <wdt.h>
  20#include <linux/delay.h>
  21
  22DECLARE_GLOBAL_DATA_PTR;
  23
  24#define SDRAM_MAX_SIZE                  (32 * 1024 * 1024)
  25
  26static const uint cs1_dram_table_66[] = {
  27        /* DRAM - single read. (offset 0 in upm RAM) */
  28        0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
  29        0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  30
  31        /* DRAM - burst read. (offset 8 in upm RAM) */
  32        0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
  33        0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
  34        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  35        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  36
  37        /* DRAM - single write. (offset 18 in upm RAM) */
  38        0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
  39        0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
  40
  41        /* DRAM - burst write. (offset 20 in upm RAM) */
  42        0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
  43        0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
  44        0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  45        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  46
  47        /* refresh  (offset 30 in upm RAM) */
  48        0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
  49        0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
  50
  51        /* init */
  52        0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
  53
  54        /* exception. (offset 3c in upm RAM) */
  55        0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  56};
  57
  58int ft_board_setup(void *blob, struct bd_info *bd)
  59{
  60        const char *sync = "receive";
  61
  62        ft_cpu_setup(blob, bd);
  63
  64        /* BRG */
  65        do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
  66                             bd->bi_busfreq, 1);
  67
  68        /* MAC addr */
  69        fdt_fixup_ethernet(blob);
  70
  71        /* Bus Frequency for CPM */
  72        do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
  73
  74        /* E1 interface - Set data rate */
  75        do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
  76
  77        /* E1 interface - Set channel phase to 0 */
  78        do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
  79
  80        /* E1 interface - rising edge sync pulse transmit */
  81        do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
  82                         sync, strlen(sync), 1);
  83
  84        return 0;
  85}
  86
  87int checkboard(void)
  88{
  89        serial_puts("BOARD: MCR3000 CSSI\n");
  90
  91        return 0;
  92}
  93
  94int dram_init(void)
  95{
  96        immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  97        memctl8xx_t __iomem *memctl = &immap->im_memctl;
  98
  99        printf("UPMA init for SDRAM (CAS latency 2), ");
 100        printf("init address 0x%08x, size ", (int)dram_init);
 101        /* Configure UPMA for cs1 */
 102        upmconfig(UPMA, (uint *)cs1_dram_table_66,
 103                  sizeof(cs1_dram_table_66) / sizeof(uint));
 104        udelay(10);
 105        out_be16(&memctl->memc_mptpr, 0x0200);
 106        out_be32(&memctl->memc_mamr, 0x14904000);
 107        udelay(10);
 108        out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
 109        out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
 110        udelay(10);
 111        out_be32(&memctl->memc_mcr, 0x80002830);
 112        out_be32(&memctl->memc_mar, 0x00000088);
 113        out_be32(&memctl->memc_mcr, 0x80002038);
 114        udelay(200);
 115
 116        gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 117                                    SDRAM_MAX_SIZE);
 118
 119        return 0;
 120}
 121
 122int misc_init_r(void)
 123{
 124        immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 125        iop8xx_t __iomem *iop = &immr->im_ioport;
 126
 127        /* Set port C13 as GPIO (BTN_ACQ_AL) */
 128        clrbits_be16(&iop->iop_pcpar, 0x4);
 129        clrbits_be16(&iop->iop_pcdir, 0x4);
 130
 131        /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
 132        if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
 133                env_set("bootdelay", "60");
 134
 135        return 0;
 136}
 137
 138int board_early_init_f(void)
 139{
 140        immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 141
 142        /*
 143         * Erase FPGA(s) for reboot
 144         */
 145        clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
 146        setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
 147        udelay(1);                              /* Wait more than 300ns */
 148        setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
 149
 150        return 0;
 151}
 152
 153int board_early_init_r(void)
 154{
 155        struct udevice *watchdog_dev = NULL;
 156
 157        if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 158                puts("Cannot find watchdog!\n");
 159        } else {
 160                puts("Enabling watchdog.\n");
 161                wdt_start(watchdog_dev, 0xffff, 0);
 162        }
 163
 164        return 0;
 165}
 166