LXR uboot/board/freescale/imx8mm_evk/imx8mm

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2018 NXP
   4 */
   5
   6#include <common.h>
   7#include <env.h>
   8#include <init.h>
   9#include <miiphy.h>
  10#include <netdev.h>
  11
  12#include <asm/arch/clock.h>
  13#include <asm/arch/sys_proto.h>
  14#include <asm/io.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18#if IS_ENABLED(CONFIG_FEC_MXC)
  19static int setup_fec(void)
  20{
  21        struct iomuxc_gpr_base_regs *gpr =
  22                (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  23
  24        /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  25        clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
  26
  27        return 0;
  28}
  29
  30int board_phy_config(struct phy_device *phydev)
  31{
  32        /* enable rgmii rxc skew and phy mode select to RGMII copper */
  33        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  34        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  35
  36        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
  37        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
  38        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  39        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  40
  41        if (phydev->drv->config)
  42                phydev->drv->config(phydev);
  43        return 0;
  44}
  45#endif
  46
  47int board_init(void)
  48{
  49        if (IS_ENABLED(CONFIG_FEC_MXC))
  50                setup_fec();
  51
  52        return 0;
  53}
  54
  55int board_mmc_get_env_dev(int devno)
  56{
  57        return devno;
  58}
  59
  60int board_late_init(void)
  61{
  62#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  63        env_set("board_name", "EVK");
  64        env_set("board_rev", "iMX8MM");
  65#endif
  66        return 0;
  67}
  68