1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2016 Freescale Semiconductor 4 */ 5 6#ifndef __CPLD_H__ 7#define __CPLD_H__ 8 9/* 10 * CPLD register set of LS1046ARDB board-specific. 11 * CPLD Revision: V2.1 12 */ 13struct cpld_data { 14 u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ 15 u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ 16 u8 pcba_ver; /* 0x2 - PCBA Revision Register */ 17 u8 system_rst; /* 0x3 - system reset register */ 18 u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ 19 u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */ 20 u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */ 21 u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */ 22 u8 sysclk_sel; /* 0x8 - System clock POR Register */ 23 u8 uart_sel; /* 0x9 - UART1 Connection Control Register */ 24 u8 sd1refclk_sel; /* 0xA - */ 25 u8 rgmii_1588_sel; /* 0xB - */ 26 u8 reg_1588_clk_sel; /* 0xC - */ 27 u8 status_led; /* 0xD - */ 28 u8 global_rst; /* 0xE - */ 29 u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */ 30 u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */ 31 u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */ 32}; 33 34u8 cpld_read(unsigned int reg); 35void cpld_write(unsigned int reg, u8 value); 36void cpld_rev_bit(unsigned char *value); 37void cpld_select_core_volt(bool en_0v9); 38 39#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 40#define CPLD_WRITE(reg, value) \ 41 cpld_write(offsetof(struct cpld_data, reg), value) 42 43/* CPLD on IFC */ 44#define CPLD_SW_MUX_BANK_SEL 0x40 45#define CPLD_BANK_SEL_MASK 0x07 46#define CPLD_BANK_SEL_ALTBANK 0x04 47#define CPLD_CFG_RCW_SRC_QSPI 0x044 48#define CPLD_CFG_RCW_SRC_SD 0x040 49#endif 50