LXR uboot/board/freescale/mpc8313erdb/sdram.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
   4 *
   5 * Authors: Nick.Spence@freescale.com
   6 *          Wilson.Lo@freescale.com
   7 *          scottwood@freescale.com
   8 */
   9
  10#include <common.h>
  11#include <init.h>
  12#include <mpc83xx.h>
  13#include <spd_sdram.h>
  14#include <linux/delay.h>
  15
  16#include <asm/bitops.h>
  17#include <asm/io.h>
  18
  19#include <asm/processor.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  24static void resume_from_sleep(void)
  25{
  26        u32 magic = *(u32 *)0;
  27
  28        typedef void (*func_t)(void);
  29        func_t resume = *(func_t *)4;
  30
  31        if (magic == 0xf5153ae5)
  32                resume();
  33
  34        gd->flags &= ~GD_FLG_SILENT;
  35        puts("\nResume from sleep failed: bad magic word\n");
  36}
  37#endif
  38
  39/* Fixed sdram init -- doesn't use serial presence detect.
  40 *
  41 * This is useful for faster booting in configs where the RAM is unlikely
  42 * to be changed, or for things like NAND booting where space is tight.
  43 */
  44static long fixed_sdram(void)
  45{
  46        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  47
  48#ifndef CONFIG_SYS_RAMBOOT
  49        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  50        u32 msize_log2 = __ilog2(msize);
  51
  52        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  53        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
  54        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  55
  56        /*
  57         * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  58         * or the DDR2 controller may fail to initialize correctly.
  59         */
  60        __udelay(50000);
  61
  62#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  63#warning Chip select bounds is only configurable in 16MB increments
  64#endif
  65        im->ddr.csbnds[0].csbnds =
  66                ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  67                (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
  68                        CSBNDS_EA);
  69        im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  70
  71        /* Currently we use only one CS, so disable the other bank. */
  72        im->ddr.cs_config[1] = 0;
  73
  74        im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
  75        im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  76        im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  77        im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  78        im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  79
  80#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  81        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  82                im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
  83        else
  84#endif
  85                im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
  86
  87        im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
  88        im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  89        im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
  90
  91        im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  92        sync();
  93
  94        /* enable DDR controller */
  95        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  96#endif
  97
  98        return msize;
  99}
 100
 101int dram_init(void)
 102{
 103        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 104        volatile fsl_lbc_t *lbc = &im->im_lbc;
 105        u32 msize;
 106
 107        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 108                return -ENXIO;
 109
 110        /* DDR SDRAM - Main SODIMM */
 111        msize = fixed_sdram();
 112
 113        /* Local Bus setup lbcr and mrtpr */
 114        lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
 115        /* LB refresh timer prescal, 266MHz/32 */
 116        lbc->mrtpr = 0x20000000;
 117        sync();
 118
 119#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
 120        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 121                resume_from_sleep();
 122#endif
 123
 124        /* return total bus SDRAM size(bytes)  -- DDR */
 125        gd->ram_size = msize;
 126
 127        return 0;
 128}
 129