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9#include <common.h>
10#include <hwconfig.h>
11#include <i2c.h>
12#include <init.h>
13#include <net.h>
14#include <linux/delay.h>
15#include <linux/libfdt.h>
16#include <fdt_support.h>
17#include <pci.h>
18#include <mpc83xx.h>
19#include <netdev.h>
20#include <asm/io.h>
21#include <ns16550.h>
22#include <nand.h>
23
24DECLARE_GLOBAL_DATA_PTR;
25
26int board_early_init_f(void)
27{
28 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
29
30 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
31 gd->flags |= GD_FLG_SILENT;
32
33 return 0;
34}
35
36#ifndef CONFIG_NAND_SPL
37
38static u8 read_board_info(void)
39{
40 u8 val8;
41 i2c_set_bus_num(0);
42
43 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
44 return val8;
45 else
46 return 0;
47}
48
49int checkboard(void)
50{
51 static const char * const rev_str[] = {
52 "0.0",
53 "0.1",
54 "1.0",
55 "1.1",
56 "<unknown>",
57 };
58 u8 info;
59 int i;
60
61 info = read_board_info();
62 i = (!info) ? 4: info & 0x03;
63
64 printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
65
66 return 0;
67}
68
69static struct pci_region pci_regions[] = {
70 {
71 bus_start: CONFIG_SYS_PCI_MEM_BASE,
72 phys_start: CONFIG_SYS_PCI_MEM_PHYS,
73 size: CONFIG_SYS_PCI_MEM_SIZE,
74 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
75 },
76 {
77 bus_start: CONFIG_SYS_PCI_MMIO_BASE,
78 phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
79 size: CONFIG_SYS_PCI_MMIO_SIZE,
80 flags: PCI_REGION_MEM
81 },
82 {
83 bus_start: CONFIG_SYS_PCI_IO_BASE,
84 phys_start: CONFIG_SYS_PCI_IO_PHYS,
85 size: CONFIG_SYS_PCI_IO_SIZE,
86 flags: PCI_REGION_IO
87 }
88};
89
90static struct pci_region pcie_regions_0[] = {
91 {
92 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
93 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
94 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
95 .flags = PCI_REGION_MEM,
96 },
97 {
98 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
99 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
100 .size = CONFIG_SYS_PCIE1_IO_SIZE,
101 .flags = PCI_REGION_IO,
102 },
103};
104
105static struct pci_region pcie_regions_1[] = {
106 {
107 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
108 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
109 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
110 .flags = PCI_REGION_MEM,
111 },
112 {
113 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
114 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
115 .size = CONFIG_SYS_PCIE2_IO_SIZE,
116 .flags = PCI_REGION_IO,
117 },
118};
119
120void pci_init_board(void)
121{
122 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
123 volatile sysconf83xx_t *sysconf = &immr->sysconf;
124 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
125 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
126 volatile law83xx_t *pcie_law = sysconf->pcielaw;
127 struct pci_region *reg[] = { pci_regions };
128 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
129
130
131 clk->occr |= 0xe0000000;
132
133
134
135
136 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
137 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
138
139 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
140 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
141
142 mpc83xx_pci_init(1, reg);
143
144
145 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
146 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
147
148
149 out_be32(&sysconf->pecr1, 0xE0008000);
150 out_be32(&sysconf->pecr2, 0xE0008000);
151 udelay(2000);
152
153
154 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
155 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
156
157 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
158 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
159
160 mpc83xx_pcie_init(2, pcie_reg);
161}
162
163#if defined(CONFIG_OF_BOARD_SETUP)
164void fdt_tsec1_fixup(void *fdt, struct bd_info *bd)
165{
166 const char disabled[] = "disabled";
167 const char *path;
168 int ret;
169
170 if (hwconfig_arg_cmp("board_type", "tsec1")) {
171 return;
172 } else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
173 printf("NOTICE: No or unknown board_type hwconfig specified.\n"
174 " Assuming board with TSEC1.\n");
175 return;
176 }
177
178 ret = fdt_path_offset(fdt, "/aliases");
179 if (ret < 0) {
180 printf("WARNING: can't find /aliases node\n");
181 return;
182 }
183
184 path = fdt_getprop(fdt, ret, "ethernet0", NULL);
185 if (!path) {
186 printf("WARNING: can't find ethernet0 alias\n");
187 return;
188 }
189
190 do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
191}
192
193int ft_board_setup(void *blob, struct bd_info *bd)
194{
195 ft_cpu_setup(blob, bd);
196#ifdef CONFIG_PCI
197 ft_pci_setup(blob, bd);
198#endif
199 fsl_fdt_fixup_dr_usb(blob, bd);
200 fdt_tsec1_fixup(blob, bd);
201
202 return 0;
203}
204#endif
205
206int board_eth_init(struct bd_info *bis)
207{
208 cpu_eth_init(bis);
209 return pci_eth_init(bis);
210}
211
212#else
213
214int checkboard(void)
215{
216 puts("Board: Freescale MPC8315ERDB\n");
217 return 0;
218}
219
220void board_init_f(ulong bootflag)
221{
222 board_early_init_f();
223 NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
224 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
225 puts("NAND boot... ");
226 timer_init();
227 dram_init();
228 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
229 CONFIG_SYS_NAND_U_BOOT_RELOC);
230}
231
232void board_init_r(gd_t *gd, ulong dest_addr)
233{
234 nand_boot();
235}
236
237void putc(char c)
238{
239 if (gd->flags & GD_FLG_SILENT)
240 return;
241
242 if (c == '\n')
243 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
244
245 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
246}
247
248#endif
249
