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7#include <common.h>
8#include <init.h>
9#include <log.h>
10#include <asm/io.h>
11#include <asm/arch/imx-regs.h>
12#include <asm/arch/sys_proto.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/iomux-mx53.h>
16#include <asm/arch/clock.h>
17#include <env.h>
18#include <linux/errno.h>
19#include <asm/mach-imx/mx5_video.h>
20#include <netdev.h>
21#include <i2c.h>
22#include <input.h>
23#include <mmc.h>
24#include <fsl_esdhc_imx.h>
25#include <asm/gpio.h>
26#include <power/pmic.h>
27#include <dialog_pmic.h>
28#include <fsl_pmic.h>
29#include <linux/fb.h>
30#include <ipu_pixfmt.h>
31
32#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
33
34DECLARE_GLOBAL_DATA_PTR;
35
36u32 get_board_rev(void)
37{
38 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
39 struct fuse_bank *bank = &iim->bank[0];
40 struct fuse_bank0_regs *fuse =
41 (struct fuse_bank0_regs *)bank->fuse_regs;
42
43 int rev = readl(&fuse->gp[6]);
44
45 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
46 rev = 0;
47
48 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
49}
50
51#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
52 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
53
54static void setup_iomux_uart(void)
55{
56 static const iomux_v3_cfg_t uart_pads[] = {
57 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
58 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
59 };
60
61 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
62}
63
64#ifdef CONFIG_USB_EHCI_MX5
65int board_ehci_hcd_init(int port)
66{
67
68 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
69 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
70 return 0;
71}
72#endif
73
74static void setup_iomux_fec(void)
75{
76 static const iomux_v3_cfg_t fec_pads[] = {
77 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
78 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
79 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
80 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
81 PAD_CTL_HYS | PAD_CTL_PKE),
82 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
83 PAD_CTL_HYS | PAD_CTL_PKE),
84 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
85 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
86 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
87 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
88 PAD_CTL_HYS | PAD_CTL_PKE),
89 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
90 PAD_CTL_HYS | PAD_CTL_PKE),
91 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
92 PAD_CTL_HYS | PAD_CTL_PKE),
93 };
94
95 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
96}
97
98#ifdef CONFIG_FSL_ESDHC_IMX
99struct fsl_esdhc_cfg esdhc_cfg[2] = {
100 {MMC_SDHC1_BASE_ADDR},
101 {MMC_SDHC3_BASE_ADDR},
102};
103
104int board_mmc_getcd(struct mmc *mmc)
105{
106 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
107 int ret;
108
109 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
110 gpio_direction_input(IMX_GPIO_NR(3, 11));
111 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
112 gpio_direction_input(IMX_GPIO_NR(3, 13));
113
114 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
115 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
116 else
117 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
118
119 return ret;
120}
121
122#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
123 PAD_CTL_PUS_100K_UP)
124#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
125 PAD_CTL_DSE_HIGH)
126
127int board_mmc_init(struct bd_info *bis)
128{
129 static const iomux_v3_cfg_t sd1_pads[] = {
130 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
131 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
132 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
133 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
134 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
135 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
136 MX53_PAD_EIM_DA13__GPIO3_13,
137 };
138
139 static const iomux_v3_cfg_t sd2_pads[] = {
140 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
141 SD_CMD_PAD_CTRL),
142 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
143 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
144 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
145 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
146 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
147 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
148 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
149 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
150 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
151 MX53_PAD_EIM_DA11__GPIO3_11,
152 };
153
154 u32 index;
155 int ret;
156
157 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
158 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
159
160 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
161 switch (index) {
162 case 0:
163 imx_iomux_v3_setup_multiple_pads(sd1_pads,
164 ARRAY_SIZE(sd1_pads));
165 break;
166 case 1:
167 imx_iomux_v3_setup_multiple_pads(sd2_pads,
168 ARRAY_SIZE(sd2_pads));
169 break;
170 default:
171 printf("Warning: you configured more ESDHC controller"
172 "(%d) as supported by the board(2)\n",
173 CONFIG_SYS_FSL_ESDHC_NUM);
174 return -EINVAL;
175 }
176 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
177 if (ret)
178 return ret;
179 }
180
181 return 0;
182}
183#endif
184
185#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
186 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
187
188static void setup_iomux_i2c(void)
189{
190 static const iomux_v3_cfg_t i2c1_pads[] = {
191 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
192 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
193 };
194
195 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
196}
197
198static int power_init(void)
199{
200 unsigned int val;
201 int ret;
202 struct pmic *p;
203
204 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
205 ret = pmic_dialog_init(I2C_PMIC);
206 if (ret)
207 return ret;
208
209 p = pmic_get("DIALOG_PMIC");
210 if (!p)
211 return -ENODEV;
212
213 env_set("fdt_file", "imx53-qsb.dtb");
214
215
216 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
217 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
218 if (ret) {
219 printf("Writing to BUCKCORE_REG failed: %d\n", ret);
220 return ret;
221 }
222
223 pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
224 val |= DA9052_SUPPLY_VBCOREGO;
225 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
226 if (ret) {
227 printf("Writing to SUPPLY_REG failed: %d\n", ret);
228 return ret;
229 }
230
231
232 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
233 if (ret) {
234 printf("Writing to BUCKPRO_REG failed: %d\n", ret);
235 return ret;
236 }
237
238 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
239 if (ret) {
240 printf("Writing to SUPPLY_REG failed: %d\n", ret);
241 return ret;
242 }
243
244 return ret;
245 }
246
247 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
248 ret = pmic_init(I2C_0);
249 if (ret)
250 return ret;
251
252 p = pmic_get("FSL_PMIC");
253 if (!p)
254 return -ENODEV;
255
256 env_set("fdt_file", "imx53-qsrb.dtb");
257
258
259 pmic_reg_read(p, REG_SW_0, &val);
260 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
261 ret = pmic_reg_write(p, REG_SW_0, val);
262 if (ret) {
263 printf("Writing to REG_SW_0 failed: %d\n", ret);
264 return ret;
265 }
266
267
268 pmic_reg_read(p, REG_SW_1, &val);
269 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
270 ret = pmic_reg_write(p, REG_SW_1, val);
271 if (ret) {
272 printf("Writing to REG_SW_1 failed: %d\n", ret);
273 return ret;
274 }
275
276
277 pmic_reg_read(p, REG_POWER_CTL2, &val);
278 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
279 ret = pmic_reg_write(p, REG_POWER_CTL2, val);
280 if (ret) {
281 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
282 return ret;
283 }
284
285
286 pmic_reg_read(p, REG_MODE_0, &val);
287 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
288 ret = pmic_reg_write(p, REG_MODE_0, val);
289 if (ret) {
290 printf("Writing to REG_MODE_0 failed: %d\n", ret);
291 return ret;
292 }
293
294
295 val = SWBST_AUTO;
296 ret = pmic_reg_write(p, SWBST_CTRL, val);
297 if (ret) {
298 printf("Writing to SWBST_CTRL failed: %d\n", ret);
299 return ret;
300 }
301
302 return ret;
303 }
304
305 return -1;
306}
307
308static void clock_1GHz(void)
309{
310 int ret;
311 u32 ref_clk = MXC_HCLK;
312
313
314
315
316 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
317 if (ret)
318 printf("CPU: Switch CPU clock to 1GHZ failed\n");
319
320 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
321 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
322 if (ret)
323 printf("CPU: Switch DDR clock to 400MHz failed\n");
324}
325
326int board_early_init_f(void)
327{
328 setup_iomux_uart();
329 setup_iomux_fec();
330 setup_iomux_lcd();
331
332 return 0;
333}
334
335
336
337
338
339int overwrite_console(void)
340{
341 return 1;
342}
343
344int board_init(void)
345{
346 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
347
348 mxc_set_sata_internal_clock();
349 setup_iomux_i2c();
350
351 return 0;
352}
353
354int board_late_init(void)
355{
356 if (!power_init())
357 clock_1GHz();
358
359 return 0;
360}
361
362int checkboard(void)
363{
364 puts("Board: MX53 LOCO\n");
365
366 return 0;
367}
368
