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5
6#include <common.h>
7#include <command.h>
8#include <env.h>
9#include <fdt_support.h>
10#include <image.h>
11#include <init.h>
12#include <netdev.h>
13#include <linux/compiler.h>
14#include <asm/mmu.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17#include <asm/immap_85xx.h>
18#include <asm/fsl_law.h>
19#include <asm/fsl_serdes.h>
20#include <asm/fsl_liodn.h>
21#include <fm_eth.h>
22
23extern void pci_of_setup(void *blob, struct bd_info *bd);
24
25#include "cpld.h"
26
27DECLARE_GLOBAL_DATA_PTR;
28
29int checkboard(void)
30{
31 u8 sw;
32 struct cpu_type *cpu = gd->arch.cpu;
33 unsigned int i;
34
35 printf("Board: %sRDB, ", cpu->name);
36 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
37 CPLD_READ(cpld_ver_sub));
38
39 sw = CPLD_READ(fbank_sel);
40 printf("vBank: %d\n", sw & 0x1);
41
42
43
44
45
46
47
48
49
50 puts("SERDES Reference Clocks: ");
51 sw = in_8(&CPLD_SW(2)) >> 2;
52 for (i = 0; i < 2; i++) {
53 static const char * const freq[][3] = {{"0", "100", "125"},
54 {"100", "156.25", "125"}
55 };
56 unsigned int clock = (sw >> (2 * i)) & 3;
57
58 printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
59 }
60 puts("\n");
61
62 return 0;
63}
64
65int board_early_init_f(void)
66{
67 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
68
69
70 setbits_be32(&gur->ddrclkdr, 0x000f000f);
71
72 return 0;
73}
74
75#define CPLD_LANE_A_SEL 0x1
76#define CPLD_LANE_G_SEL 0x2
77#define CPLD_LANE_C_SEL 0x4
78#define CPLD_LANE_D_SEL 0x8
79
80void board_config_lanes_mux(void)
81{
82 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
83 int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
84 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
85
86 u8 mux = 0;
87 switch (srds_prtcl) {
88 case 0x2:
89 case 0x5:
90 case 0x9:
91 case 0xa:
92 case 0xf:
93 break;
94 case 0x8:
95 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
96 break;
97 case 0x14:
98 mux |= CPLD_LANE_A_SEL;
99 break;
100 case 0x17:
101 mux |= CPLD_LANE_G_SEL;
102 break;
103 case 0x16:
104 case 0x19:
105 case 0x1a:
106 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
107 break;
108 case 0x1c:
109 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
110 break;
111 default:
112 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
113 break;
114 }
115 CPLD_WRITE(serdes_mux, mux);
116}
117
118int board_early_init_r(void)
119{
120 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
121 int flash_esel = find_tlb_idx((void *)flashbase, 1);
122
123
124
125
126
127
128
129 flush_dcache();
130 invalidate_icache();
131
132 if (flash_esel == -1) {
133
134 puts("Error: Could not find TLB for FLASH BASE\n");
135 flash_esel = 2;
136 } else {
137
138 disable_tlb(flash_esel);
139 }
140
141 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
142 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
143 0, flash_esel, BOOKE_PAGESZ_256M, 1);
144
145 board_config_lanes_mux();
146
147 return 0;
148}
149
150unsigned long get_board_sys_clk(unsigned long dummy)
151{
152 u8 sysclk_conf = CPLD_READ(sysclk_sw1);
153
154 switch (sysclk_conf & 0x7) {
155 case CPLD_SYSCLK_83:
156 return 83333333;
157 case CPLD_SYSCLK_100:
158 return 100000000;
159 default:
160 return 66666666;
161 }
162}
163
164#define NUM_SRDS_BANKS 2
165
166int misc_init_r(void)
167{
168 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
169 u32 actual[NUM_SRDS_BANKS];
170 unsigned int i;
171 u8 sw;
172 static const int freq[][3] = {
173 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
174 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
175 SRDS_PLLCR0_RFCK_SEL_125}
176 };
177
178 sw = in_8(&CPLD_SW(2)) >> 2;
179 for (i = 0; i < NUM_SRDS_BANKS; i++) {
180 unsigned int clock = (sw >> (2 * i)) & 3;
181 if (clock == 0x3) {
182 printf("Warning: SDREFCLK%u switch setting of '11' is "
183 "unsupported\n", i + 1);
184 break;
185 }
186 if (i == 0 && clock == 0)
187 puts("Warning: SDREFCLK1 switch setting of"
188 "'00' is unsupported\n");
189 else
190 actual[i] = freq[i][clock];
191
192
193
194
195
196
197 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
198 (CPLD_READ(pcba_ver) == 5)) {
199
200 actual[i] = freq[i-1][clock];
201 }
202 }
203
204 for (i = 0; i < NUM_SRDS_BANKS; i++) {
205 u32 expected = in_be32(®s->bank[i].pllcr0);
206 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
207 if (expected != actual[i]) {
208 printf("Warning: SERDES bank %u expects reference clock"
209 " %sMHz, but actual is %sMHz\n", i + 1,
210 serdes_clock_to_string(expected),
211 serdes_clock_to_string(actual[i]));
212 }
213 }
214
215 return 0;
216}
217
218int ft_board_setup(void *blob, struct bd_info *bd)
219{
220 phys_addr_t base;
221 phys_size_t size;
222
223 ft_cpu_setup(blob, bd);
224
225 base = env_get_bootm_low();
226 size = env_get_bootm_size();
227
228 fdt_fixup_memory(blob, (u64)base, (u64)size);
229
230#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
231 fsl_fdt_fixup_dr_usb(blob, bd);
232#endif
233
234#ifdef CONFIG_PCI
235 pci_of_setup(blob, bd);
236#endif
237
238 fdt_fixup_liodn(blob);
239#ifdef CONFIG_SYS_DPAA_FMAN
240#ifndef CONFIG_DM_ETH
241 fdt_fixup_fman_ethernet(blob);
242#endif
243#endif
244
245 return 0;
246}
247