LXR uboot/board/freescale/t208xqds/ddr.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright 2013 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <i2c.h>
   8#include <hwconfig.h>
   9#include <init.h>
  10#include <log.h>
  11#include <asm/mmu.h>
  12#include <fsl_ddr_sdram.h>
  13#include <fsl_ddr_dimm_params.h>
  14#include <asm/fsl_law.h>
  15#include "ddr.h"
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19void fsl_ddr_board_options(memctl_options_t *popts,
  20                                dimm_params_t *pdimm,
  21                                unsigned int ctrl_num)
  22{
  23        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  24        ulong ddr_freq;
  25
  26        if (ctrl_num > 1) {
  27                printf("Not supported controller number %d\n", ctrl_num);
  28                return;
  29        }
  30        if (!pdimm->n_ranks)
  31                return;
  32
  33        /*
  34         * we use identical timing for all slots. If needed, change the code
  35         * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  36         */
  37        if (popts->registered_dimm_en)
  38                pbsp = rdimms[0];
  39        else
  40                pbsp = udimms[0];
  41
  42        /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  43         * freqency and n_banks specified in board_specific_parameters table.
  44         */
  45        ddr_freq = get_ddr_freq(0) / 1000000;
  46        while (pbsp->datarate_mhz_high) {
  47                if (pbsp->n_ranks == pdimm->n_ranks &&
  48                    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  49                        if (ddr_freq <= pbsp->datarate_mhz_high) {
  50                                popts->clk_adjust = pbsp->clk_adjust;
  51                                popts->wrlvl_start = pbsp->wrlvl_start;
  52                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  53                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  54                                goto found;
  55                        }
  56                        pbsp_highest = pbsp;
  57                }
  58                pbsp++;
  59        }
  60
  61        if (pbsp_highest) {
  62                printf("Error: board specific timing not found");
  63                printf("for data rate %lu MT/s\n", ddr_freq);
  64                printf("Trying to use the highest speed (%u) parameters\n",
  65                       pbsp_highest->datarate_mhz_high);
  66                popts->clk_adjust = pbsp_highest->clk_adjust;
  67                popts->wrlvl_start = pbsp_highest->wrlvl_start;
  68                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  69                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  70        } else {
  71                panic("DIMM is not supported by this board");
  72        }
  73found:
  74        debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  75                "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  76                "wrlvl_ctrl_3 0x%x\n",
  77                pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  78                pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  79                pbsp->wrlvl_ctl_3);
  80
  81        /*
  82         * Factors to consider for half-strength driver enable:
  83         *      - number of DIMMs installed
  84         */
  85        popts->half_strength_driver_enable = 0;
  86        /*
  87         * Write leveling override
  88         */
  89        popts->wrlvl_override = 1;
  90        popts->wrlvl_sample = 0xf;
  91
  92        /*
  93         * Rtt and Rtt_WR override
  94         */
  95        popts->rtt_override = 0;
  96
  97        /* Enable ZQ calibration */
  98        popts->zq_en = 1;
  99
 100        /* DHC_EN =1, ODT = 75 Ohm */
 101        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 102        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 103
 104        /* optimize cpo for erratum A-009942 */
 105        popts->cpo_sample = 0x64;
 106}
 107
 108int dram_init(void)
 109{
 110        phys_size_t dram_size;
 111
 112#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 113        puts("Initializing....using SPD\n");
 114        dram_size = fsl_ddr_sdram();
 115#else
 116        /* DDR has been initialised by first stage boot loader */
 117        dram_size =  fsl_ddr_sdram_size();
 118#endif
 119        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 120        dram_size *= 0x100000;
 121
 122        gd->ram_size = dram_size;
 123
 124        return 0;
 125}
 126