1/* SPDX-License-Identifier: GPL-2.0+ */ 2/** 3 * Copyright 2014 Freescale Semiconductor 4 * 5 * Author: Chunhe Lan <Chunhe.Lan@freescale.com> 6 * 7 * This file provides support for the ngPIXIS, a board-specific FPGA used on 8 * some Freescale reference boards. 9 */ 10 11/* 12 * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 13 */ 14struct cpld_data { 15 u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ 16 u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ 17 u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ 18 u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ 19 u8 hw_ver; /* 0x04 - PCBA Version Register */ 20 u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ 21 u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ 22 u8 res0; /* 0x07 - not used */ 23 u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ 24 u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ 25 u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ 26 u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ 27 u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ 28 u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ 29 u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ 30 u8 res1; /* 0x0f - not used */ 31}; 32 33#define CPLD_BANK_SEL_MASK 0x07 34#define CPLD_BANK_SEL_EN 0x04 35#define CPLD_SYSTEM_RESET 0x01 36#define CPLD_SELECT_BANK0 0x00 37#define CPLD_SELECT_BANK4 0x04 38#define CPLD_DEFAULT_BANK 0x01 39 40/* Pointer to the CPLD register set */ 41 42u8 cpld_read(unsigned int reg); 43void cpld_write(unsigned int reg, u8 value); 44 45#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 46#define CPLD_WRITE(reg, value) \ 47 cpld_write(offsetof(struct cpld_data, reg), value) 48 49