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7#include <common.h>
8#include <env.h>
9#include <flash.h>
10#include <hwconfig.h>
11#include <i2c.h>
12#include <init.h>
13#include <spi.h>
14#include <linux/bitops.h>
15#include <linux/delay.h>
16#include <linux/libfdt.h>
17#include <fdt_support.h>
18#include <pci.h>
19#include <mpc83xx.h>
20#include <fsl_esdhc.h>
21#include <asm/io.h>
22#include <asm/fsl_serdes.h>
23#include <asm/fsl_mpc83xx_serdes.h>
24
25#include "mpc8308.h"
26
27#include <gdsys_fpga.h>
28
29#include "../common/adv7611.h"
30#include "../common/ch7301.h"
31#include "../common/dp501.h"
32#include "../common/ioep-fpga.h"
33#include "../common/mclink.h"
34#include "../common/osd.h"
35#include "../common/phy.h"
36#include "../common/fanctrl.h"
37
38#include <pca953x.h>
39#include <pca9698.h>
40
41#include <miiphy.h>
42
43#define MAX_MUX_CHANNELS 2
44
45enum {
46 MCFPGA_DONE = 1 << 0,
47 MCFPGA_INIT_N = 1 << 1,
48 MCFPGA_PROGRAM_N = 1 << 2,
49 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
50 MCFPGA_RESET_N = 1 << 4,
51};
52
53enum {
54 GPIO_MDC = 1 << 14,
55 GPIO_MDIO = 1 << 15,
56};
57
58uint mclink_fpgacount;
59struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
60
61struct {
62 u8 bus;
63 u8 addr;
64} strider_fans[] = CONFIG_STRIDER_FANS;
65
66int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
67{
68 int res;
69
70 switch (fpga) {
71 case 0:
72 out_le16(reg, data);
73 break;
74 default:
75 res = mclink_send(fpga - 1, regoff, data);
76 if (res < 0) {
77 printf("mclink_send reg %02lx data %04x returned %d\n",
78 regoff, data, res);
79 return res;
80 }
81 break;
82 }
83
84 return 0;
85}
86
87int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
88{
89 int res;
90
91 switch (fpga) {
92 case 0:
93 *data = in_le16(reg);
94 break;
95 default:
96 if (fpga > mclink_fpgacount)
97 return -EINVAL;
98 res = mclink_receive(fpga - 1, regoff, data);
99 if (res < 0) {
100 printf("mclink_receive reg %02lx returned %d\n",
101 regoff, res);
102 return res;
103 }
104 }
105
106 return 0;
107}
108
109int checkboard(void)
110{
111 char *s = env_get("serial#");
112 bool hw_type_cat = pca9698_get_value(0x20, 18);
113
114 puts("Board: ");
115
116 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
117
118 if (s) {
119 puts(", serial# ");
120 puts(s);
121 }
122
123 puts("\n");
124
125 return 0;
126}
127
128int last_stage_init(void)
129{
130 int slaves;
131 uint k;
132 uint mux_ch;
133 uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
134#ifdef CONFIG_STRIDER_CPU
135 uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
136#endif
137 bool hw_type_cat = pca9698_get_value(0x20, 18);
138#ifdef CONFIG_STRIDER_CON_DP
139 bool is_dh = pca9698_get_value(0x20, 25);
140#endif
141 bool ch0_sgmii2_present;
142
143
144 pca9698_direction_output(0x20, 8, 0);
145
146
147 pca9698_direction_output(0x20, 10, 1);
148 pca9698_direction_output(0x20, 11, 1);
149
150 ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
151
152
153 for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
154 uint ctr = 0;
155 uchar *mclink_controllers = mclink_controllers_dvi;
156
157#ifdef CONFIG_STRIDER_CPU
158 if (i2c_probe(mclink_controllers[k])) {
159 mclink_controllers = mclink_controllers_dp;
160 if (i2c_probe(mclink_controllers[k]))
161 continue;
162 }
163#else
164 if (i2c_probe(mclink_controllers[k]))
165 continue;
166#endif
167 while (!(pca953x_get_val(mclink_controllers[k])
168 & MCFPGA_DONE)) {
169 mdelay(100);
170 if (ctr++ > 5) {
171 printf("no done for mclink_controller %d\n", k);
172 break;
173 }
174 }
175
176 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
177 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
178 udelay(10);
179 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
180 MCFPGA_RESET_N);
181 }
182
183 if (hw_type_cat) {
184 int retval;
185 struct mii_dev *mdiodev = mdio_alloc();
186
187 if (!mdiodev)
188 return -ENOMEM;
189 strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
190 mdiodev->read = bb_miiphy_read;
191 mdiodev->write = bb_miiphy_write;
192
193 retval = mdio_register(mdiodev);
194 if (retval < 0)
195 return retval;
196 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
197 if ((mux_ch == 1) && !ch0_sgmii2_present)
198 continue;
199
200 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
201 }
202 }
203
204
205 mdelay(500);
206
207 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
208 slaves = mclink_probe();
209 mclink_fpgacount = 0;
210
211 ioep_fpga_print_info(0);
212
213 if (!adv7611_probe(0))
214 printf(" Advantiv ADV7611 HDMI Receiver\n");
215
216#ifdef CONFIG_STRIDER_CON
217 if (ioep_fpga_has_osd(0))
218 osd_probe(0);
219#endif
220
221#ifdef CONFIG_STRIDER_CON_DP
222 if (ioep_fpga_has_osd(0)) {
223 osd_probe(0);
224 if (is_dh)
225 osd_probe(4);
226 }
227#endif
228
229#ifdef CONFIG_STRIDER_CPU
230 ch7301_probe(0, false);
231 dp501_probe(0, false);
232#endif
233
234 if (slaves <= 0)
235 return 0;
236
237 mclink_fpgacount = slaves;
238
239#ifdef CONFIG_STRIDER_CPU
240
241 for (k = 1; k <= slaves; ++k)
242 FPGA_SET_REG(k, extended_control, 0x10);
243
244 mdelay(500);
245#endif
246
247 for (k = 1; k <= slaves; ++k) {
248 ioep_fpga_print_info(k);
249#ifdef CONFIG_STRIDER_CON
250 if (ioep_fpga_has_osd(k))
251 osd_probe(k);
252#endif
253#ifdef CONFIG_STRIDER_CON_DP
254 if (ioep_fpga_has_osd(k)) {
255 osd_probe(k);
256 if (is_dh)
257 osd_probe(k + 4);
258 }
259#endif
260#ifdef CONFIG_STRIDER_CPU
261 if (!adv7611_probe(k))
262 printf(" Advantiv ADV7611 HDMI Receiver\n");
263 ch7301_probe(k, false);
264 dp501_probe(k, false);
265#endif
266 if (hw_type_cat) {
267 int retval;
268 struct mii_dev *mdiodev = mdio_alloc();
269
270 if (!mdiodev)
271 return -ENOMEM;
272 strncpy(mdiodev->name, bb_miiphy_buses[k].name,
273 MDIO_NAME_LEN);
274 mdiodev->read = bb_miiphy_read;
275 mdiodev->write = bb_miiphy_write;
276
277 retval = mdio_register(mdiodev);
278 if (retval < 0)
279 return retval;
280 setup_88e1514(bb_miiphy_buses[k].name, 0);
281 }
282 }
283
284 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
285 i2c_set_bus_num(strider_fans[k].bus);
286 init_fan_controller(strider_fans[k].addr);
287 }
288
289 return 0;
290}
291
292
293
294
295
296void fpga_gpio_set(uint bus, int pin)
297{
298 FPGA_SET_REG(bus, gpio.set, pin);
299}
300
301void fpga_gpio_clear(uint bus, int pin)
302{
303 FPGA_SET_REG(bus, gpio.clear, pin);
304}
305
306int fpga_gpio_get(uint bus, int pin)
307{
308 u16 val;
309
310 FPGA_GET_REG(bus, gpio.read, &val);
311
312 return val & pin;
313}
314
315#ifdef CONFIG_STRIDER_CON_DP
316void fpga_control_set(uint bus, int pin)
317{
318 u16 val;
319
320 FPGA_GET_REG(bus, control, &val);
321 FPGA_SET_REG(bus, control, val | pin);
322}
323
324void fpga_control_clear(uint bus, int pin)
325{
326 u16 val;
327
328 FPGA_GET_REG(bus, control, &val);
329 FPGA_SET_REG(bus, control, val & ~pin);
330}
331#endif
332
333void mpc8308_init(void)
334{
335 pca9698_direction_output(0x20, 26, 1);
336}
337
338void mpc8308_set_fpga_reset(uint state)
339{
340 pca9698_set_value(0x20, 26, state ? 0 : 1);
341}
342
343void mpc8308_setup_hw(void)
344{
345 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
346
347
348
349
350 setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
351 setbits_gpio0_out(BIT(31 - 12));
352}
353
354int mpc8308_get_fpga_done(uint fpga)
355{
356 return pca9698_get_value(0x20, 20);
357}
358
359#ifdef CONFIG_FSL_ESDHC
360int board_mmc_init(struct bd_info *bd)
361{
362 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
363 sysconf83xx_t *sysconf = &immr->sysconf;
364
365
366 out_be32(&sysconf->sdhccr, 0x02000000);
367
368 return fsl_esdhc_mmc_init(bd);
369}
370#endif
371
372static struct pci_region pcie_regions_0[] = {
373 {
374 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
375 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
376 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
377 .flags = PCI_REGION_MEM,
378 },
379 {
380 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
381 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
382 .size = CONFIG_SYS_PCIE1_IO_SIZE,
383 .flags = PCI_REGION_IO,
384 },
385};
386
387void pci_init_board(void)
388{
389 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
390 sysconf83xx_t *sysconf = &immr->sysconf;
391 law83xx_t *pcie_law = sysconf->pcielaw;
392 struct pci_region *pcie_reg[] = { pcie_regions_0 };
393
394 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
395 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
396
397
398 out_be32(&sysconf->pecr1, 0xE0008000);
399 udelay(2000);
400
401
402 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
403 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
404
405 mpc83xx_pcie_init(1, pcie_reg);
406}
407
408ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
409{
410 info->portwidth = FLASH_CFI_16BIT;
411 info->chipwidth = FLASH_CFI_BY16;
412 info->interface = FLASH_CFI_X16;
413 return 1;
414}
415
416#if defined(CONFIG_OF_BOARD_SETUP)
417int ft_board_setup(void *blob, struct bd_info *bd)
418{
419 ft_cpu_setup(blob, bd);
420 fsl_fdt_fixup_dr_usb(blob, bd);
421 fdt_fixup_esdhc(blob, bd);
422
423 return 0;
424}
425#endif
426
427
428
429
430
431struct fpga_mii {
432 uint fpga;
433 int mdio;
434} fpga_mii[] = {
435 { 0, 1},
436 { 1, 1},
437 { 2, 1},
438 { 3, 1},
439};
440
441static int mii_dummy_init(struct bb_miiphy_bus *bus)
442{
443 return 0;
444}
445
446static int mii_mdio_active(struct bb_miiphy_bus *bus)
447{
448 struct fpga_mii *fpga_mii = bus->priv;
449
450 if (fpga_mii->mdio)
451 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
452 else
453 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
454
455 return 0;
456}
457
458static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
459{
460 struct fpga_mii *fpga_mii = bus->priv;
461
462 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
463
464 return 0;
465}
466
467static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
468{
469 struct fpga_mii *fpga_mii = bus->priv;
470
471 if (v)
472 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
473 else
474 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
475
476 fpga_mii->mdio = v;
477
478 return 0;
479}
480
481static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
482{
483 u16 gpio;
484 struct fpga_mii *fpga_mii = bus->priv;
485
486 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
487
488 *v = ((gpio & GPIO_MDIO) != 0);
489
490 return 0;
491}
492
493static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
494{
495 struct fpga_mii *fpga_mii = bus->priv;
496
497 if (v)
498 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
499 else
500 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
501
502 return 0;
503}
504
505static int mii_delay(struct bb_miiphy_bus *bus)
506{
507 udelay(1);
508
509 return 0;
510}
511
512struct bb_miiphy_bus bb_miiphy_buses[] = {
513 {
514 .name = "board0",
515 .init = mii_dummy_init,
516 .mdio_active = mii_mdio_active,
517 .mdio_tristate = mii_mdio_tristate,
518 .set_mdio = mii_set_mdio,
519 .get_mdio = mii_get_mdio,
520 .set_mdc = mii_set_mdc,
521 .delay = mii_delay,
522 .priv = &fpga_mii[0],
523 },
524 {
525 .name = "board1",
526 .init = mii_dummy_init,
527 .mdio_active = mii_mdio_active,
528 .mdio_tristate = mii_mdio_tristate,
529 .set_mdio = mii_set_mdio,
530 .get_mdio = mii_get_mdio,
531 .set_mdc = mii_set_mdc,
532 .delay = mii_delay,
533 .priv = &fpga_mii[1],
534 },
535 {
536 .name = "board2",
537 .init = mii_dummy_init,
538 .mdio_active = mii_mdio_active,
539 .mdio_tristate = mii_mdio_tristate,
540 .set_mdio = mii_set_mdio,
541 .get_mdio = mii_get_mdio,
542 .set_mdc = mii_set_mdc,
543 .delay = mii_delay,
544 .priv = &fpga_mii[2],
545 },
546 {
547 .name = "board3",
548 .init = mii_dummy_init,
549 .mdio_active = mii_mdio_active,
550 .mdio_tristate = mii_mdio_tristate,
551 .set_mdio = mii_set_mdio,
552 .get_mdio = mii_get_mdio,
553 .set_mdc = mii_set_mdc,
554 .delay = mii_delay,
555 .priv = &fpga_mii[3],
556 },
557};
558
559int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
560
