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7#include <common.h>
8#include <dm.h>
9#include <fdt_support.h>
10#include <init.h>
11#include <log.h>
12#include <asm/io.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/imx-regs.h>
15#include <asm/arch/iomux.h>
16#include <asm/arch/mx6-pins.h>
17#include <asm/arch/mx6-ddr.h>
18#include <asm/arch/sys_proto.h>
19#include <env.h>
20#include <errno.h>
21#include <asm/gpio.h>
22#include <malloc.h>
23#include <asm/mach-imx/iomux-v3.h>
24#include <asm/mach-imx/boot_mode.h>
25#include <miiphy.h>
26#include <netdev.h>
27#include <i2c.h>
28#include <linux/delay.h>
29
30#include <dm/platform_data/serial_mxc.h>
31#include <dm/platdata.h>
32
33#include "common.h"
34
35DECLARE_GLOBAL_DATA_PTR;
36
37static bool hw_ids_valid;
38static bool sw_ids_valid;
39static u32 cpu_id;
40static u32 unit_id;
41
42const char *gpio_table_sw_names[] = {
43 "GPIO2_4", "GPIO2_5", "GPIO2_6", "GPIO2_7"
44};
45
46const char *gpio_table_sw_ids_names[] = {
47 "sw0", "sw1", "sw2", "sw3"
48};
49
50const char *gpio_table_hw_names[] = {
51 "GPIO6_7", "GPIO6_9", "GPIO6_10", "GPIO6_11",
52 "GPIO4_7", "GPIO4_11", "GPIO4_13", "GPIO4_15"
53};
54
55const char *gpio_table_hw_ids_names[] = {
56 "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
57};
58
59static int get_board_id(const char **pin_names, const char **ids_names,
60 int size, bool *valid, u32 *id)
61{
62 struct gpio_desc desc;
63 int i, ret, val;
64
65 *valid = false;
66
67 for (i = 0; i < size; i++) {
68 memset(&desc, 0, sizeof(desc));
69
70 ret = dm_gpio_lookup_name(pin_names[i], &desc);
71 if (ret) {
72 printf("Can't lookup request SWx gpios\n");
73 return ret;
74 }
75
76 ret = dm_gpio_request(&desc, ids_names[i]);
77 if (ret) {
78 printf("Can't lookup request SWx gpios\n");
79 return ret;
80 }
81
82 dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
83
84 val = dm_gpio_get_value(&desc);
85 if (val < 0) {
86 printf("Can't get SW%d ID\n", i);
87 *id = 0;
88 return val;
89 }
90 *id |= val << i;
91 }
92 *valid = true;
93
94 return 0;
95}
96
97int dram_init(void)
98{
99 gd->ram_size = imx_ddr_size();
100
101 return 0;
102}
103
104iomux_v3_cfg_t const misc_pads[] = {
105
106 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
107 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
108 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
109 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
110
111
112 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
113 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
114 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
115 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
116 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
117 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
118 MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
119 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
120
121
122 MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
123
124
125 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
126};
127
128
129
130
131
132int overwrite_console(void)
133{
134 return 1;
135}
136
137#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
138int ft_board_setup(void *blob, struct bd_info *bd)
139{
140 fdt_fixup_ethernet(blob);
141 return 0;
142}
143#endif
144
145int board_phy_config(struct phy_device *phydev)
146{
147
148 phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
149 ADVERTISED_1000baseX_Full |
150 SUPPORTED_1000baseT_Half |
151 SUPPORTED_1000baseT_Full);
152
153 if (phydev->drv->config)
154 return phydev->drv->config(phydev);
155
156 return 0;
157}
158
159int board_init(void)
160{
161 struct gpio_desc phy_int_gbe, spi2_wp;
162 int ret;
163
164 debug("board init\n");
165
166 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
167
168
169 SETUP_IOMUX_PADS(misc_pads);
170
171 get_board_id(gpio_table_sw_names, &gpio_table_sw_ids_names[0],
172 ARRAY_SIZE(gpio_table_sw_names), &sw_ids_valid, &unit_id);
173 debug("SWx unit_id 0x%x\n", unit_id);
174
175 get_board_id(gpio_table_hw_names, &gpio_table_hw_ids_names[0],
176 ARRAY_SIZE(gpio_table_hw_names), &hw_ids_valid, &cpu_id);
177 debug("HWx cpu_id 0x%x\n", cpu_id);
178
179 if (hw_ids_valid && sw_ids_valid)
180 printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
181
182 udelay(25);
183
184
185 ret = dm_gpio_lookup_name("GPIO1_28", &phy_int_gbe);
186 if (ret) {
187 printf("Cannot get GPIO1_28\n");
188 } else {
189 ret = dm_gpio_request(&phy_int_gbe, "INT_GBE");
190 if (!ret)
191 dm_gpio_set_dir_flags(&phy_int_gbe, GPIOD_IS_IN);
192 }
193
194 iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
195 enable_fec_anatop_clock(0, ENET_125MHZ);
196
197
198 ret = dm_gpio_lookup_name("GPIO7_0", &spi2_wp);
199 if (ret) {
200 printf("Cannot get GPIO7_0\n");
201 } else {
202 ret = dm_gpio_request(&spi2_wp, "spi2_#wp");
203 if (!ret)
204 dm_gpio_set_dir_flags(&spi2_wp, GPIOD_IS_OUT |
205 GPIOD_IS_OUT_ACTIVE);
206 }
207
208 return 0;
209}
210
211#ifdef CONFIG_CMD_BMODE
212static const struct boot_mode board_boot_modes[] = {
213
214
215 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
216 {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
217 {NULL, 0},
218};
219
220static void setup_boot_modes(void)
221{
222 add_board_boot_modes(board_boot_modes);
223}
224#else
225static inline void setup_boot_modes(void) {}
226#endif
227
228int misc_init_r(void)
229{
230 struct gpio_desc em_pad;
231 int ret;
232
233 setup_boot_modes();
234
235 ret = dm_gpio_lookup_name("GPIO3_29", &em_pad);
236 if (ret) {
237 printf("Can't find emergency PAD gpio\n");
238 return ret;
239 }
240
241 ret = dm_gpio_request(&em_pad, "Emergency_PAD");
242 if (ret) {
243 printf("Can't request emergency PAD gpio\n");
244 return ret;
245 }
246
247 dm_gpio_set_dir_flags(&em_pad, GPIOD_IS_IN);
248
249 return 0;
250}
251
