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6#include <common.h>
7#include <cpu.h>
8#include <dm.h>
9#include <thermal.h>
10#include <asm/system.h>
11#include <asm/arch/sci/sci.h>
12#include <asm/arch/sys_proto.h>
13#include <asm/arch-imx/cpu.h>
14#include <asm/armv8/cpu.h>
15#include <linux/bitops.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19struct cpu_imx_platdata {
20 const char *name;
21 const char *rev;
22 const char *type;
23 u32 cpu_rsrc;
24 u32 cpurev;
25 u32 freq_mhz;
26 u32 mpidr;
27};
28
29const char *get_imx8_type(u32 imxtype)
30{
31 switch (imxtype) {
32 case MXC_CPU_IMX8QXP:
33 case MXC_CPU_IMX8QXP_A0:
34 return "QXP";
35 case MXC_CPU_IMX8QM:
36 return "QM";
37 default:
38 return "??";
39 }
40}
41
42const char *get_imx8_rev(u32 rev)
43{
44 switch (rev) {
45 case CHIP_REV_A:
46 return "A";
47 case CHIP_REV_B:
48 return "B";
49 case CHIP_REV_C:
50 return "C";
51 default:
52 return "?";
53 }
54}
55
56static void set_core_data(struct udevice *dev)
57{
58 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
59
60 if (device_is_compatible(dev, "arm,cortex-a35")) {
61 plat->cpu_rsrc = SC_R_A35;
62 plat->name = "A35";
63 } else if (device_is_compatible(dev, "arm,cortex-a53")) {
64 plat->cpu_rsrc = SC_R_A53;
65 plat->name = "A53";
66 } else if (device_is_compatible(dev, "arm,cortex-a72")) {
67 plat->cpu_rsrc = SC_R_A72;
68 plat->name = "A72";
69 } else {
70 plat->cpu_rsrc = SC_R_A53;
71 plat->name = "?";
72 }
73}
74
75#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
76static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
77{
78 struct udevice *thermal_dev;
79 int cpu_tmp, ret;
80 int idx = 1;
81
82 if (plat->cpu_rsrc == SC_R_A72)
83 idx = 2;
84
85 ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev);
86 if (!ret) {
87 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
88 if (ret)
89 return 0xdeadbeef;
90 } else {
91 return 0xdeadbeef;
92 }
93
94 return cpu_tmp;
95}
96#else
97static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
98{
99 return 0;
100}
101#endif
102
103int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
104{
105 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
106 int ret, temp;
107
108 if (size < 100)
109 return -ENOSPC;
110
111 ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
112 plat->type, plat->rev, plat->name, plat->freq_mhz);
113
114 if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
115 temp = cpu_imx_get_temp(plat);
116 buf = buf + ret;
117 size = size - ret;
118 if (temp != 0xdeadbeef)
119 ret = snprintf(buf, size, " at %dC", temp);
120 else
121 ret = snprintf(buf, size, " - invalid sensor data");
122 }
123
124 snprintf(buf + ret, size - ret, "\n");
125
126 return 0;
127}
128
129static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
130{
131 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
132
133 info->cpu_freq = plat->freq_mhz * 1000;
134 info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
135 return 0;
136}
137
138static int cpu_imx_get_count(const struct udevice *dev)
139{
140 ofnode node;
141 int num = 0;
142
143 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
144 const char *device_type;
145
146 if (!ofnode_is_available(node))
147 continue;
148
149 device_type = ofnode_read_string(node, "device_type");
150 if (!device_type)
151 continue;
152
153 if (!strcmp(device_type, "cpu"))
154 num++;
155 }
156
157 return num;
158}
159
160static int cpu_imx_get_vendor(const struct udevice *dev, char *buf, int size)
161{
162 snprintf(buf, size, "NXP");
163 return 0;
164}
165
166static int cpu_imx_is_current(struct udevice *dev)
167{
168 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
169
170 if (plat->mpidr == (read_mpidr() & 0xffff))
171 return 1;
172
173 return 0;
174}
175
176static const struct cpu_ops cpu_imx8_ops = {
177 .get_desc = cpu_imx_get_desc,
178 .get_info = cpu_imx_get_info,
179 .get_count = cpu_imx_get_count,
180 .get_vendor = cpu_imx_get_vendor,
181 .is_current = cpu_imx_is_current,
182};
183
184static const struct udevice_id cpu_imx8_ids[] = {
185 { .compatible = "arm,cortex-a35" },
186 { .compatible = "arm,cortex-a53" },
187 { .compatible = "arm,cortex-a72" },
188 { }
189};
190
191static ulong imx8_get_cpu_rate(struct udevice *dev)
192{
193 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
194 ulong rate;
195 int ret;
196
197 ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
198 (sc_pm_clock_rate_t *)&rate);
199 if (ret) {
200 printf("Could not read CPU frequency: %d\n", ret);
201 return 0;
202 }
203
204 return rate;
205}
206
207static int imx8_cpu_probe(struct udevice *dev)
208{
209 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
210 u32 cpurev;
211
212 set_core_data(dev);
213 cpurev = get_cpu_rev();
214 plat->cpurev = cpurev;
215 plat->rev = get_imx8_rev(cpurev & 0xFFF);
216 plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
217 plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000;
218 plat->mpidr = dev_read_addr(dev);
219 if (plat->mpidr == FDT_ADDR_T_NONE) {
220 printf("%s: Failed to get CPU reg property\n", __func__);
221 return -EINVAL;
222 }
223
224 return 0;
225}
226
227U_BOOT_DRIVER(cpu_imx8_drv) = {
228 .name = "imx8x_cpu",
229 .id = UCLASS_CPU,
230 .of_match = cpu_imx8_ids,
231 .ops = &cpu_imx8_ops,
232 .probe = imx8_cpu_probe,
233 .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata),
234 .flags = DM_FLAG_PRE_RELOC,
235};
236
