1
2
3
4
5
6#include <common.h>
7#include <log.h>
8#include <asm/io.h>
9#include <asm/arch/sdram.h>
10#include <errno.h>
11#include <hang.h>
12#include "sequencer.h"
13
14static const struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
15 (struct socfpga_sdr_rw_load_manager *)
16 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
17static const struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs
18 = (struct socfpga_sdr_rw_load_jump_manager *)
19 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
20static const struct socfpga_sdr_reg_file *sdr_reg_file =
21 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
22static const struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
23 (struct socfpga_sdr_scc_mgr *)
24 (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
25static const struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
26 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
27static const struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
28 (struct socfpga_phy_mgr_cfg *)
29 (SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
30static const struct socfpga_data_mgr *data_mgr =
31 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
32static const struct socfpga_sdr_ctrl *sdr_ctrl =
33 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
34
35#define DELTA_D 1
36
37
38
39
40
41
42
43
44
45
46
47
48
49#define DLEVEL 0
50#define STATIC_IN_RTL_SIM 0
51#define STATIC_SKIP_DELAY_LOOPS 0
52
53#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
54 STATIC_SKIP_DELAY_LOOPS)
55
56#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
57 ((non_skip_value) & seq->skip_delay_mask)
58
59bool dram_is_ddr(const u8 ddr)
60{
61 const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
62 const u8 type = (cfg->ctrl_cfg >> SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) &
63 SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK;
64
65 if (ddr == 2 && type == 1)
66 return true;
67
68 if (ddr == 3 && type == 2)
69 return true;
70
71 return false;
72}
73
74static void set_failing_group_stage(struct socfpga_sdrseq *seq,
75 u32 group, u32 stage, u32 substage)
76{
77
78
79
80
81 if (seq->gbl.error_stage == CAL_STAGE_NIL) {
82 seq->gbl.error_substage = substage;
83 seq->gbl.error_stage = stage;
84 seq->gbl.error_group = group;
85 }
86}
87
88static void reg_file_set_group(u16 set_group)
89{
90 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
91}
92
93static void reg_file_set_stage(u8 set_stage)
94{
95 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
96}
97
98static void reg_file_set_sub_stage(u8 set_sub_stage)
99{
100 set_sub_stage &= 0xff;
101 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
102}
103
104
105
106
107
108
109static void phy_mgr_initialize(struct socfpga_sdrseq *seq)
110{
111 u32 ratio;
112
113 debug("%s:%d\n", __func__, __LINE__);
114
115
116
117
118
119
120 writel(0x3, &phy_mgr_cfg->mux_sel);
121
122
123 writel(0, &phy_mgr_cfg->reset_mem_stbl);
124
125
126 writel(0, &phy_mgr_cfg->cal_status);
127
128 writel(0, &phy_mgr_cfg->cal_debug_info);
129
130
131 if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
132 return;
133
134 ratio = seq->rwcfg->mem_dq_per_read_dqs /
135 seq->rwcfg->mem_virtual_groups_per_read_dqs;
136 seq->param.read_correct_mask_vg = (1 << ratio) - 1;
137 seq->param.write_correct_mask_vg = (1 << ratio) - 1;
138 seq->param.read_correct_mask = (1 << seq->rwcfg->mem_dq_per_read_dqs)
139 - 1;
140 seq->param.write_correct_mask = (1 << seq->rwcfg->mem_dq_per_write_dqs)
141 - 1;
142}
143
144
145
146
147
148
149
150
151static void set_rank_and_odt_mask(struct socfpga_sdrseq *seq,
152 const u32 rank, const u32 odt_mode)
153{
154 u32 odt_mask_0 = 0;
155 u32 odt_mask_1 = 0;
156 u32 cs_and_odt_mask;
157
158 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
159 odt_mask_0 = 0x0;
160 odt_mask_1 = 0x0;
161 } else {
162 switch (seq->rwcfg->mem_number_of_ranks) {
163 case 1:
164
165 odt_mask_0 = 0x0;
166 odt_mask_1 = 0x1;
167 break;
168 case 2:
169 if (seq->rwcfg->mem_number_of_cs_per_dimm == 1) {
170
171
172
173
174
175
176
177
178
179
180
181
182 odt_mask_0 = 0x3 & ~(1 << rank);
183 odt_mask_1 = 0x3;
184 if (dram_is_ddr(2))
185 odt_mask_1 &= ~(1 << rank);
186 } else {
187
188
189
190
191
192
193 odt_mask_0 = 0x0;
194 odt_mask_1 = 0x3 & (1 << rank);
195 }
196 break;
197 case 4:
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223 switch (rank) {
224 case 0:
225 odt_mask_0 = 0x4;
226 if (dram_is_ddr(2))
227 odt_mask_1 = 0x4;
228 else if (dram_is_ddr(3))
229 odt_mask_1 = 0x5;
230 break;
231 case 1:
232 odt_mask_0 = 0x8;
233 if (dram_is_ddr(2))
234 odt_mask_1 = 0x8;
235 else if (dram_is_ddr(3))
236 odt_mask_1 = 0xA;
237 break;
238 case 2:
239 odt_mask_0 = 0x1;
240 if (dram_is_ddr(2))
241 odt_mask_1 = 0x1;
242 else if (dram_is_ddr(3))
243 odt_mask_1 = 0x5;
244 break;
245 case 3:
246 odt_mask_0 = 0x2;
247 if (dram_is_ddr(2))
248 odt_mask_1 = 0x2;
249 else if (dram_is_ddr(3))
250 odt_mask_1 = 0xA;
251 break;
252 }
253 break;
254 }
255 }
256
257 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
258 ((0xFF & odt_mask_0) << 8) |
259 ((0xFF & odt_mask_1) << 16);
260 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
261 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
262}
263
264
265
266
267
268
269
270
271
272static void scc_mgr_set(u32 off, u32 grp, u32 val)
273{
274 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
275}
276
277
278
279
280
281
282static void scc_mgr_initialize(void)
283{
284
285
286
287
288
289
290 int i;
291
292 for (i = 0; i < 16; i++) {
293 debug_cond(DLEVEL >= 1, "%s:%d: Clearing SCC RFILE index %u\n",
294 __func__, __LINE__, i);
295 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
296 }
297}
298
299static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase)
300{
301 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
302}
303
304static void scc_mgr_set_dqs_bus_in_delay(u32 read_group, u32 delay)
305{
306 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
307}
308
309static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase)
310{
311 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
312}
313
314static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay)
315{
316 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
317}
318
319static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
320{
321 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
322}
323
324static void scc_mgr_set_dqs_io_in_delay(struct socfpga_sdrseq *seq,
325 u32 delay)
326{
327 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
328 seq->rwcfg->mem_dq_per_write_dqs, delay);
329}
330
331static void scc_mgr_set_dm_in_delay(struct socfpga_sdrseq *seq, u32 dm,
332 u32 delay)
333{
334 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
335 seq->rwcfg->mem_dq_per_write_dqs + 1 + dm,
336 delay);
337}
338
339static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
340{
341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
342}
343
344static void scc_mgr_set_dqs_out1_delay(struct socfpga_sdrseq *seq,
345 u32 delay)
346{
347 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
348 seq->rwcfg->mem_dq_per_write_dqs, delay);
349}
350
351static void scc_mgr_set_dm_out1_delay(struct socfpga_sdrseq *seq, u32 dm,
352 u32 delay)
353{
354 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
355 seq->rwcfg->mem_dq_per_write_dqs + 1 + dm,
356 delay);
357}
358
359
360static void scc_mgr_load_dqs(u32 dqs)
361{
362 writel(dqs, &sdr_scc_mgr->dqs_ena);
363}
364
365
366static void scc_mgr_load_dqs_io(void)
367{
368 writel(0, &sdr_scc_mgr->dqs_io_ena);
369}
370
371
372static void scc_mgr_load_dq(u32 dq_in_group)
373{
374 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
375}
376
377
378static void scc_mgr_load_dm(u32 dm)
379{
380 writel(dm, &sdr_scc_mgr->dm_ena);
381}
382
383
384
385
386
387
388
389
390
391
392
393static void scc_mgr_set_all_ranks(struct socfpga_sdrseq *seq,
394 const u32 off, const u32 grp, const u32 val,
395 const int update)
396{
397 u32 r;
398
399 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
400 r += NUM_RANKS_PER_SHADOW_REG) {
401 scc_mgr_set(off, grp, val);
402
403 if (update || (r == 0)) {
404 writel(grp, &sdr_scc_mgr->dqs_ena);
405 writel(0, &sdr_scc_mgr->update);
406 }
407 }
408}
409
410static void scc_mgr_set_dqs_en_phase_all_ranks(struct socfpga_sdrseq *seq,
411 u32 read_group, u32 phase)
412{
413
414
415
416
417
418
419
420
421 scc_mgr_set_all_ranks(seq, SCC_MGR_DQS_EN_PHASE_OFFSET,
422 read_group, phase, 0);
423}
424
425static void scc_mgr_set_dqdqs_output_phase_all_ranks(struct socfpga_sdrseq *seq,
426 u32 write_group, u32 phase)
427{
428
429
430
431
432
433
434
435
436 scc_mgr_set_all_ranks(seq, SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
437 write_group, phase, 0);
438}
439
440static void scc_mgr_set_dqs_en_delay_all_ranks(struct socfpga_sdrseq *seq,
441 u32 read_group, u32 delay)
442{
443
444
445
446
447
448
449
450
451 scc_mgr_set_all_ranks(seq, SCC_MGR_DQS_EN_DELAY_OFFSET,
452 read_group, delay, 1);
453}
454
455
456
457
458
459
460
461
462static void scc_mgr_set_oct_out1_delay(struct socfpga_sdrseq *seq,
463 const u32 write_group, const u32 delay)
464{
465 const int ratio = seq->rwcfg->mem_if_read_dqs_width /
466 seq->rwcfg->mem_if_write_dqs_width;
467 const int base = write_group * ratio;
468 int i;
469
470
471
472
473
474
475
476 for (i = 0; i < ratio; i++)
477 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
478}
479
480
481
482
483
484
485static void scc_mgr_set_hhp_extras(void)
486{
487
488
489
490
491
492
493
494
495
496 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
497 (1 << 2) | (1 << 1) | (1 << 0);
498 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
499 SCC_MGR_HHP_GLOBALS_OFFSET |
500 SCC_MGR_HHP_EXTRAS_OFFSET;
501
502 debug_cond(DLEVEL >= 1, "%s:%d Setting HHP Extras\n",
503 __func__, __LINE__);
504 writel(value, addr);
505 debug_cond(DLEVEL >= 1, "%s:%d Done Setting HHP Extras\n",
506 __func__, __LINE__);
507}
508
509
510
511
512
513
514static void scc_mgr_zero_all(struct socfpga_sdrseq *seq)
515{
516 int i, r;
517
518
519
520
521
522 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
523 r += NUM_RANKS_PER_SHADOW_REG) {
524 for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
525
526
527
528
529
530 scc_mgr_set_dqs_bus_in_delay(i,
531 seq->iocfg->dqs_in_reserve
532 );
533 scc_mgr_set_dqs_en_phase(i, 0);
534 scc_mgr_set_dqs_en_delay(i, 0);
535 }
536
537 for (i = 0; i < seq->rwcfg->mem_if_write_dqs_width; i++) {
538 scc_mgr_set_dqdqs_output_phase(i, 0);
539
540 scc_mgr_set_oct_out1_delay(seq, i,
541 seq->iocfg->dqs_out_reserve);
542 }
543 }
544
545
546 writel(0xff, &sdr_scc_mgr->dqs_ena);
547 writel(0, &sdr_scc_mgr->update);
548}
549
550
551
552
553
554
555
556static void scc_set_bypass_mode(const u32 write_group)
557{
558
559 writel(0xff, &sdr_scc_mgr->dq_ena);
560 writel(0xff, &sdr_scc_mgr->dm_ena);
561
562
563 writel(0, &sdr_scc_mgr->dqs_io_ena);
564
565
566 writel(write_group, &sdr_scc_mgr->dqs_ena);
567
568
569 writel(0, &sdr_scc_mgr->update);
570}
571
572
573
574
575
576
577
578static void scc_mgr_load_dqs_for_write_group(struct socfpga_sdrseq *seq,
579 const u32 write_group)
580{
581 const int ratio = seq->rwcfg->mem_if_read_dqs_width /
582 seq->rwcfg->mem_if_write_dqs_width;
583 const int base = write_group * ratio;
584 int i;
585
586
587
588
589
590
591
592 for (i = 0; i < ratio; i++)
593 writel(base + i, &sdr_scc_mgr->dqs_ena);
594}
595
596
597
598
599
600
601static void scc_mgr_zero_group(struct socfpga_sdrseq *seq,
602 const u32 write_group, const int out_only)
603{
604 int i, r;
605
606 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
607 r += NUM_RANKS_PER_SHADOW_REG) {
608
609 for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) {
610 scc_mgr_set_dq_out1_delay(i, 0);
611 if (!out_only)
612 scc_mgr_set_dq_in_delay(i, 0);
613 }
614
615
616 writel(0xff, &sdr_scc_mgr->dq_ena);
617
618
619 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
620 if (!out_only)
621 scc_mgr_set_dm_in_delay(seq, i, 0);
622 scc_mgr_set_dm_out1_delay(seq, i, 0);
623 }
624
625
626 writel(0xff, &sdr_scc_mgr->dm_ena);
627
628
629 if (!out_only)
630 scc_mgr_set_dqs_io_in_delay(seq, 0);
631
632
633 scc_mgr_set_dqs_out1_delay(seq, seq->iocfg->dqs_out_reserve);
634 scc_mgr_set_oct_out1_delay(seq, write_group,
635 seq->iocfg->dqs_out_reserve);
636 scc_mgr_load_dqs_for_write_group(seq, write_group);
637
638
639 writel(0, &sdr_scc_mgr->dqs_io_ena);
640
641
642 writel(0, &sdr_scc_mgr->update);
643 }
644}
645
646
647
648
649
650static void scc_mgr_apply_group_dq_in_delay(struct socfpga_sdrseq *seq,
651 u32 group_bgn, u32 delay)
652{
653 u32 i, p;
654
655 for (i = 0, p = group_bgn; i < seq->rwcfg->mem_dq_per_read_dqs;
656 i++, p++) {
657 scc_mgr_set_dq_in_delay(p, delay);
658 scc_mgr_load_dq(p);
659 }
660}
661
662
663
664
665
666
667
668
669static void scc_mgr_apply_group_dq_out1_delay(struct socfpga_sdrseq *seq,
670 const u32 delay)
671{
672 int i;
673
674 for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) {
675 scc_mgr_set_dq_out1_delay(i, delay);
676 scc_mgr_load_dq(i);
677 }
678}
679
680
681static void scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdrseq *seq,
682 u32 delay1)
683{
684 u32 i;
685
686 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
687 scc_mgr_set_dm_out1_delay(seq, i, delay1);
688 scc_mgr_load_dm(i);
689 }
690}
691
692
693
694static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq,
695 u32 write_group, u32 delay)
696{
697 scc_mgr_set_dqs_out1_delay(seq, delay);
698 scc_mgr_load_dqs_io();
699
700 scc_mgr_set_oct_out1_delay(seq, write_group, delay);
701 scc_mgr_load_dqs_for_write_group(seq, write_group);
702}
703
704
705
706
707
708
709
710
711
712static void scc_mgr_apply_group_all_out_delay_add(struct socfpga_sdrseq *seq,
713 const u32 write_group,
714 const u32 delay)
715{
716 u32 i, new_delay;
717
718
719 for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++)
720 scc_mgr_load_dq(i);
721
722
723 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
724 scc_mgr_load_dm(i);
725
726
727 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
728 if (new_delay > seq->iocfg->io_out2_delay_max) {
729 debug_cond(DLEVEL >= 1,
730 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
731 __func__, __LINE__, write_group, delay, new_delay,
732 seq->iocfg->io_out2_delay_max,
733 new_delay - seq->iocfg->io_out2_delay_max);
734 new_delay -= seq->iocfg->io_out2_delay_max;
735 scc_mgr_set_dqs_out1_delay(seq, new_delay);
736 }
737
738 scc_mgr_load_dqs_io();
739
740
741 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
742 if (new_delay > seq->iocfg->io_out2_delay_max) {
743 debug_cond(DLEVEL >= 1,
744 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
745 __func__, __LINE__, write_group, delay,
746 new_delay, seq->iocfg->io_out2_delay_max,
747 new_delay - seq->iocfg->io_out2_delay_max);
748 new_delay -= seq->iocfg->io_out2_delay_max;
749 scc_mgr_set_oct_out1_delay(seq, write_group, new_delay);
750 }
751
752 scc_mgr_load_dqs_for_write_group(seq, write_group);
753}
754
755
756
757
758
759
760
761
762
763static void
764scc_mgr_apply_group_all_out_delay_add_all_ranks(struct socfpga_sdrseq *seq,
765 const u32 write_group,
766 const u32 delay)
767{
768 int r;
769
770 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
771 r += NUM_RANKS_PER_SHADOW_REG) {
772 scc_mgr_apply_group_all_out_delay_add(seq, write_group, delay);
773 writel(0, &sdr_scc_mgr->update);
774 }
775}
776
777
778
779
780
781
782
783static void set_jump_as_return(struct socfpga_sdrseq *seq)
784{
785
786
787
788
789
790 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
791 writel(seq->rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
792}
793
794
795
796
797
798
799
800static void delay_for_n_mem_clocks(struct socfpga_sdrseq *seq,
801 const u32 clocks)
802{
803 u32 afi_clocks;
804 u16 c_loop;
805 u8 inner;
806 u8 outer;
807
808 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
809
810
811 afi_clocks = DIV_ROUND_UP(clocks, seq->misccfg->afi_rate_ratio);
812 if (afi_clocks)
813 afi_clocks--;
814
815
816
817
818
819
820
821
822 c_loop = afi_clocks >> 16;
823 outer = c_loop ? 0xff : (afi_clocks >> 8);
824 inner = outer ? 0xff : afi_clocks;
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843 if (afi_clocks < 0x100) {
844 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
845 &sdr_rw_load_mgr_regs->load_cntr1);
846
847 writel(seq->rwcfg->idle_loop1,
848 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
849
850 writel(seq->rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
851 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
852 } else {
853 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
854 &sdr_rw_load_mgr_regs->load_cntr0);
855
856 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
857 &sdr_rw_load_mgr_regs->load_cntr1);
858
859 writel(seq->rwcfg->idle_loop2,
860 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
861
862 writel(seq->rwcfg->idle_loop2,
863 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
864
865 do {
866 writel(seq->rwcfg->idle_loop2,
867 SDR_PHYGRP_RWMGRGRP_ADDRESS |
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
869 } while (c_loop-- != 0);
870 }
871 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
872}
873
874static void delay_for_n_ns(struct socfpga_sdrseq *seq, const u32 ns)
875{
876 delay_for_n_mem_clocks(seq, (ns * seq->misccfg->afi_clk_freq *
877 seq->misccfg->afi_rate_ratio) / 1000);
878}
879
880
881
882
883
884
885
886
887
888
889static void rw_mgr_mem_init_load_regs(struct socfpga_sdrseq *seq,
890 u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
891{
892 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
893 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
894
895
896 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
897 &sdr_rw_load_mgr_regs->load_cntr0);
898 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
899 &sdr_rw_load_mgr_regs->load_cntr1);
900 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
901 &sdr_rw_load_mgr_regs->load_cntr2);
902
903
904 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
905 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
906 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
907
908
909 writel(jump, grpaddr);
910}
911
912
913
914
915
916
917
918static void rw_mgr_mem_load_user_ddr2(struct socfpga_sdrseq *seq,
919 const int handoff)
920{
921 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
922 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
923 u32 r;
924
925 for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) {
926
927 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF);
928
929
930 writel(seq->rwcfg->precharge_all, grpaddr);
931
932 writel(seq->rwcfg->emr2, grpaddr);
933 writel(seq->rwcfg->emr3, grpaddr);
934 writel(seq->rwcfg->emr, grpaddr);
935
936 if (handoff) {
937 writel(seq->rwcfg->mr_user, grpaddr);
938 continue;
939 }
940
941 writel(seq->rwcfg->mr_dll_reset, grpaddr);
942
943 writel(seq->rwcfg->precharge_all, grpaddr);
944
945 writel(seq->rwcfg->refresh, grpaddr);
946 delay_for_n_ns(seq, 200);
947 writel(seq->rwcfg->refresh, grpaddr);
948 delay_for_n_ns(seq, 200);
949
950 writel(seq->rwcfg->mr_calib, grpaddr);
951 writel(0x0b, grpaddr);
952 writel(seq->rwcfg->emr, grpaddr);
953 delay_for_n_mem_clocks(seq, 200);
954 }
955}
956
957
958
959
960
961
962
963
964
965static void rw_mgr_mem_load_user_ddr3(struct socfpga_sdrseq *seq,
966 const u32 fin1, const u32 fin2,
967 const int precharge)
968{
969 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
970 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
971 u32 r;
972
973 for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) {
974
975 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF);
976
977
978 if (precharge)
979 writel(seq->rwcfg->precharge_all, grpaddr);
980
981
982
983
984
985 if ((seq->rwcfg->mem_address_mirroring >> r) & 0x1) {
986 set_jump_as_return(seq);
987 writel(seq->rwcfg->mrs2_mirr, grpaddr);
988 delay_for_n_mem_clocks(seq, 4);
989 set_jump_as_return(seq);
990 writel(seq->rwcfg->mrs3_mirr, grpaddr);
991 delay_for_n_mem_clocks(seq, 4);
992 set_jump_as_return(seq);
993 writel(seq->rwcfg->mrs1_mirr, grpaddr);
994 delay_for_n_mem_clocks(seq, 4);
995 set_jump_as_return(seq);
996 writel(fin1, grpaddr);
997 } else {
998 set_jump_as_return(seq);
999 writel(seq->rwcfg->mrs2, grpaddr);
1000 delay_for_n_mem_clocks(seq, 4);
1001 set_jump_as_return(seq);
1002 writel(seq->rwcfg->mrs3, grpaddr);
1003 delay_for_n_mem_clocks(seq, 4);
1004 set_jump_as_return(seq);
1005 writel(seq->rwcfg->mrs1, grpaddr);
1006 set_jump_as_return(seq);
1007 writel(fin2, grpaddr);
1008 }
1009
1010 if (precharge)
1011 continue;
1012
1013 set_jump_as_return(seq);
1014 writel(seq->rwcfg->zqcl, grpaddr);
1015
1016
1017 delay_for_n_mem_clocks(seq, 512);
1018 }
1019}
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029static void rw_mgr_mem_load_user(struct socfpga_sdrseq *seq,
1030 const u32 fin1, const u32 fin2,
1031 const int precharge)
1032{
1033 if (dram_is_ddr(2))
1034 rw_mgr_mem_load_user_ddr2(seq, precharge);
1035 else if (dram_is_ddr(3))
1036 rw_mgr_mem_load_user_ddr3(seq, fin1, fin2, precharge);
1037 else
1038 hang();
1039}
1040
1041
1042
1043
1044
1045static void rw_mgr_mem_initialize(struct socfpga_sdrseq *seq)
1046{
1047 debug("%s:%d\n", __func__, __LINE__);
1048
1049
1050 if (dram_is_ddr(3)) {
1051 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1052 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
1053 }
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078 rw_mgr_mem_init_load_regs(seq, seq->misccfg->tinit_cntr0_val,
1079 seq->misccfg->tinit_cntr1_val,
1080 seq->misccfg->tinit_cntr2_val,
1081 seq->rwcfg->init_reset_0_cke_0);
1082
1083
1084 writel(1, &phy_mgr_cfg->reset_mem_stbl);
1085
1086 if (dram_is_ddr(2)) {
1087 writel(seq->rwcfg->nop, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1088 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1089
1090
1091
1092
1093 delay_for_n_ns(seq, 400);
1094 } else if (dram_is_ddr(3)) {
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109 rw_mgr_mem_init_load_regs(seq, seq->misccfg->treset_cntr0_val,
1110 seq->misccfg->treset_cntr1_val,
1111 seq->misccfg->treset_cntr2_val,
1112 seq->rwcfg->init_reset_1_cke_0);
1113
1114
1115
1116 delay_for_n_mem_clocks(seq, 250);
1117 }
1118
1119 rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_dll_reset_mirr,
1120 seq->rwcfg->mrs0_dll_reset, 0);
1121}
1122
1123
1124
1125
1126
1127
1128
1129static void rw_mgr_mem_handoff(struct socfpga_sdrseq *seq)
1130{
1131 rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_user_mirr,
1132 seq->rwcfg->mrs0_user, 1);
1133
1134
1135
1136
1137
1138}
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148static void rw_mgr_mem_calibrate_write_test_issue(struct socfpga_sdrseq *seq,
1149 u32 group, u32 test_dm)
1150{
1151 const u32 quick_write_mode =
1152 (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
1153 seq->misccfg->enable_super_quick_calibration;
1154 u32 mcc_instruction;
1155 u32 rw_wl_nop_cycles;
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183 rw_wl_nop_cycles = seq->gbl.rw_wl_nop_cycles;
1184
1185 if (rw_wl_nop_cycles == -1) {
1186
1187
1188
1189
1190
1191
1192 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1193
1194
1195 if (test_dm) {
1196 mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0_wl_1;
1197 writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_data,
1198 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1199 writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_nop,
1200 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1201 } else {
1202 mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0_wl_1;
1203 writel(seq->rwcfg->lfsr_wr_rd_bank_0_data,
1204 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1205 writel(seq->rwcfg->lfsr_wr_rd_bank_0_nop,
1206 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1207 }
1208 } else if (rw_wl_nop_cycles == 0) {
1209
1210
1211
1212
1213
1214 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1215
1216
1217 if (test_dm) {
1218 mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0;
1219 writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_dqs,
1220 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1221 } else {
1222 mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0;
1223 writel(seq->rwcfg->lfsr_wr_rd_bank_0_dqs,
1224 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1225 }
1226 } else {
1227
1228
1229
1230
1231
1232 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
1233 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1234
1235
1236
1237
1238
1239 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
1240 if (test_dm) {
1241 mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0;
1242 writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_nop,
1243 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1244 } else {
1245 mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0;
1246 writel(seq->rwcfg->lfsr_wr_rd_bank_0_nop,
1247 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1248 }
1249 }
1250
1251 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1252 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1253
1254 if (quick_write_mode)
1255 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
1256 else
1257 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
1258
1259 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1260
1261
1262
1263
1264
1265 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
1266
1267 if (test_dm) {
1268 writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_wait,
1269 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1270 } else {
1271 writel(seq->rwcfg->lfsr_wr_rd_bank_0_wait,
1272 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1273 }
1274
1275 writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
1276 RW_MGR_RUN_SINGLE_GROUP_OFFSET) +
1277 (group << 2));
1278}
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292static int
1293rw_mgr_mem_calibrate_write_test(struct socfpga_sdrseq *seq,
1294 const u32 rank_bgn, const u32 write_group,
1295 const u32 use_dm, const u32 all_correct,
1296 u32 *bit_chk, const u32 all_ranks)
1297{
1298 const u32 rank_end = all_ranks ?
1299 seq->rwcfg->mem_number_of_ranks :
1300 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1301 const u32 shift_ratio = seq->rwcfg->mem_dq_per_write_dqs /
1302 seq->rwcfg->mem_virtual_groups_per_write_dqs;
1303 const u32 correct_mask_vg = seq->param.write_correct_mask_vg;
1304
1305 u32 tmp_bit_chk, base_rw_mgr, group;
1306 int vg, r;
1307
1308 *bit_chk = seq->param.write_correct_mask;
1309
1310 for (r = rank_bgn; r < rank_end; r++) {
1311
1312 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
1313
1314 tmp_bit_chk = 0;
1315 for (vg = seq->rwcfg->mem_virtual_groups_per_write_dqs - 1;
1316 vg >= 0; vg--) {
1317
1318 writel(0, &phy_mgr_cmd->fifo_reset);
1319
1320 group = write_group *
1321 seq->rwcfg->mem_virtual_groups_per_write_dqs
1322 + vg;
1323 rw_mgr_mem_calibrate_write_test_issue(seq, group,
1324 use_dm);
1325
1326 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1327 tmp_bit_chk <<= shift_ratio;
1328 tmp_bit_chk |= (correct_mask_vg & ~(base_rw_mgr));
1329 }
1330
1331 *bit_chk &= tmp_bit_chk;
1332 }
1333
1334 set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
1335 if (all_correct) {
1336 debug_cond(DLEVEL >= 2,
1337 "write_test(%u,%u,ALL) : %u == %u => %i\n",
1338 write_group, use_dm, *bit_chk,
1339 seq->param.write_correct_mask,
1340 *bit_chk == seq->param.write_correct_mask);
1341 return *bit_chk == seq->param.write_correct_mask;
1342 } else {
1343 debug_cond(DLEVEL >= 2,
1344 "write_test(%u,%u,ONE) : %u != %i => %i\n",
1345 write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
1346 return *bit_chk != 0x00;
1347 }
1348}
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359static int
1360rw_mgr_mem_calibrate_read_test_patterns(struct socfpga_sdrseq *seq,
1361 const u32 rank_bgn, const u32 group,
1362 const u32 all_ranks)
1363{
1364 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1365 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1366 const u32 addr_offset =
1367 (group * seq->rwcfg->mem_virtual_groups_per_read_dqs)
1368 << 2;
1369 const u32 rank_end = all_ranks ?
1370 seq->rwcfg->mem_number_of_ranks :
1371 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1372 const u32 shift_ratio = seq->rwcfg->mem_dq_per_read_dqs /
1373 seq->rwcfg->mem_virtual_groups_per_read_dqs;
1374 const u32 correct_mask_vg = seq->param.read_correct_mask_vg;
1375
1376 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1377 int vg, r;
1378 int ret = 0;
1379
1380 bit_chk = seq->param.read_correct_mask;
1381
1382 for (r = rank_bgn; r < rank_end; r++) {
1383
1384 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
1385
1386
1387 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1388 writel(seq->rwcfg->guaranteed_read,
1389 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1390
1391 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1392 writel(seq->rwcfg->guaranteed_read_cont,
1393 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1394
1395 tmp_bit_chk = 0;
1396 for (vg = seq->rwcfg->mem_virtual_groups_per_read_dqs - 1;
1397 vg >= 0; vg--) {
1398
1399 writel(0, &phy_mgr_cmd->fifo_reset);
1400 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1401 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1402 writel(seq->rwcfg->guaranteed_read,
1403 addr + addr_offset + (vg << 2));
1404
1405 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1406 tmp_bit_chk <<= shift_ratio;
1407 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1408 }
1409
1410 bit_chk &= tmp_bit_chk;
1411 }
1412
1413 writel(seq->rwcfg->clear_dqs_enable, addr + (group << 2));
1414
1415 set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
1416
1417 if (bit_chk != seq->param.read_correct_mask)
1418 ret = -EIO;
1419
1420 debug_cond(DLEVEL >= 1,
1421 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1422 __func__, __LINE__, group, bit_chk,
1423 seq->param.read_correct_mask, ret);
1424
1425 return ret;
1426}
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436static void rw_mgr_mem_calibrate_read_load_patterns(struct socfpga_sdrseq *seq,
1437 const u32 rank_bgn,
1438 const int all_ranks)
1439{
1440 const u32 rank_end = all_ranks ?
1441 seq->rwcfg->mem_number_of_ranks :
1442 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1443 u32 r;
1444
1445 debug("%s:%d\n", __func__, __LINE__);
1446
1447 for (r = rank_bgn; r < rank_end; r++) {
1448
1449 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
1450
1451
1452 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1453
1454 writel(seq->rwcfg->guaranteed_write_wait0,
1455 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1456
1457 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1458
1459 writel(seq->rwcfg->guaranteed_write_wait1,
1460 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1461
1462 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1463
1464 writel(seq->rwcfg->guaranteed_write_wait2,
1465 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1466
1467 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1468
1469 writel(seq->rwcfg->guaranteed_write_wait3,
1470 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1471
1472 writel(seq->rwcfg->guaranteed_write,
1473 SDR_PHYGRP_RWMGRGRP_ADDRESS |
1474 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1475 }
1476
1477 set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
1478}
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494static int
1495rw_mgr_mem_calibrate_read_test(struct socfpga_sdrseq *seq,
1496 const u32 rank_bgn, const u32 group,
1497 const u32 num_tries, const u32 all_correct,
1498 u32 *bit_chk,
1499 const u32 all_groups, const u32 all_ranks)
1500{
1501 const u32 rank_end = all_ranks ? seq->rwcfg->mem_number_of_ranks :
1502 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1503 const u32 quick_read_mode =
1504 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1505 seq->misccfg->enable_super_quick_calibration);
1506 u32 correct_mask_vg = seq->param.read_correct_mask_vg;
1507 u32 tmp_bit_chk;
1508 u32 base_rw_mgr;
1509 u32 addr;
1510
1511 int r, vg, ret;
1512
1513 *bit_chk = seq->param.read_correct_mask;
1514
1515 for (r = rank_bgn; r < rank_end; r++) {
1516
1517 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
1518
1519 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1520
1521 writel(seq->rwcfg->read_b2b_wait1,
1522 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1523
1524 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1525 writel(seq->rwcfg->read_b2b_wait2,
1526 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1527
1528 if (quick_read_mode)
1529 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1530
1531 else if (all_groups)
1532 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1533 else
1534 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1535
1536 writel(seq->rwcfg->read_b2b,
1537 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1538 if (all_groups)
1539 writel(seq->rwcfg->mem_if_read_dqs_width *
1540 seq->rwcfg->mem_virtual_groups_per_read_dqs - 1,
1541 &sdr_rw_load_mgr_regs->load_cntr3);
1542 else
1543 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1544
1545 writel(seq->rwcfg->read_b2b,
1546 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1547
1548 tmp_bit_chk = 0;
1549 for (vg = seq->rwcfg->mem_virtual_groups_per_read_dqs - 1;
1550 vg >= 0; vg--) {
1551
1552 writel(0, &phy_mgr_cmd->fifo_reset);
1553 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1554 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1555
1556 if (all_groups) {
1557 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1558 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1559 } else {
1560 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1561 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1562 }
1563
1564 writel(seq->rwcfg->read_b2b, addr +
1565 ((group *
1566 seq->rwcfg->mem_virtual_groups_per_read_dqs +
1567 vg) << 2));
1568
1569 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1570 tmp_bit_chk <<=
1571 seq->rwcfg->mem_dq_per_read_dqs /
1572 seq->rwcfg->mem_virtual_groups_per_read_dqs;
1573 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
1574 }
1575
1576 *bit_chk &= tmp_bit_chk;
1577 }
1578
1579 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1580 writel(seq->rwcfg->clear_dqs_enable, addr + (group << 2));
1581
1582 set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
1583
1584 if (all_correct) {
1585 ret = (*bit_chk == seq->param.read_correct_mask);
1586 debug_cond(DLEVEL >= 2,
1587 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1588 __func__, __LINE__, group, all_groups, *bit_chk,
1589 seq->param.read_correct_mask, ret);
1590 } else {
1591 ret = (*bit_chk != 0x00);
1592 debug_cond(DLEVEL >= 2,
1593 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1594 __func__, __LINE__, group, all_groups, *bit_chk,
1595 0, ret);
1596 }
1597
1598 return ret;
1599}
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610static int
1611rw_mgr_mem_calibrate_read_test_all_ranks(struct socfpga_sdrseq *seq,
1612 const u32 grp, const u32 num_tries,
1613 const u32 all_correct,
1614 const u32 all_groups)
1615{
1616 u32 bit_chk;
1617 return rw_mgr_mem_calibrate_read_test(seq, 0, grp, num_tries,
1618 all_correct, &bit_chk, all_groups,
1619 1);
1620}
1621
1622
1623
1624
1625
1626
1627
1628static void rw_mgr_incr_vfifo(const u32 grp)
1629{
1630 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1631}
1632
1633
1634
1635
1636
1637
1638
1639static void rw_mgr_decr_vfifo(struct socfpga_sdrseq *seq, const u32 grp)
1640{
1641 u32 i;
1642
1643 for (i = 0; i < seq->misccfg->read_valid_fifo_size - 1; i++)
1644 rw_mgr_incr_vfifo(grp);
1645}
1646
1647
1648
1649
1650
1651
1652
1653static int find_vfifo_failing_read(struct socfpga_sdrseq *seq,
1654 const u32 grp)
1655{
1656 u32 v, ret, fail_cnt = 0;
1657
1658 for (v = 0; v < seq->misccfg->read_valid_fifo_size; v++) {
1659 debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n",
1660 __func__, __LINE__, v);
1661 ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
1662 PASS_ONE_BIT, 0);
1663 if (!ret) {
1664 fail_cnt++;
1665
1666 if (fail_cnt == 2)
1667 return v;
1668 }
1669
1670
1671 rw_mgr_incr_vfifo(grp);
1672 }
1673
1674
1675 debug_cond(DLEVEL >= 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1676 return 0;
1677}
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690static int sdr_find_phase_delay(struct socfpga_sdrseq *seq, int working,
1691 int delay, const u32 grp, u32 *work,
1692 const u32 work_inc, u32 *pd)
1693{
1694 const u32 max = delay ? seq->iocfg->dqs_en_delay_max :
1695 seq->iocfg->dqs_en_phase_max;
1696 u32 ret;
1697
1698 for (; *pd <= max; (*pd)++) {
1699 if (delay)
1700 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, *pd);
1701 else
1702 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *pd);
1703
1704 ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
1705 PASS_ONE_BIT, 0);
1706 if (!working)
1707 ret = !ret;
1708
1709 if (ret)
1710 return 0;
1711
1712 if (work)
1713 *work += work_inc;
1714 }
1715
1716 return -EINVAL;
1717}
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728static int sdr_find_phase(struct socfpga_sdrseq *seq, int working,
1729 const u32 grp, u32 *work, u32 *i, u32 *p)
1730{
1731 const u32 end = seq->misccfg->read_valid_fifo_size + (working ? 0 : 1);
1732 int ret;
1733
1734 for (; *i < end; (*i)++) {
1735 if (working)
1736 *p = 0;
1737
1738 ret = sdr_find_phase_delay(seq, working, 0, grp, work,
1739 seq->iocfg->delay_per_opa_tap, p);
1740 if (!ret)
1741 return 0;
1742
1743 if (*p > seq->iocfg->dqs_en_phase_max) {
1744
1745 rw_mgr_incr_vfifo(grp);
1746 if (!working)
1747 *p = 0;
1748 }
1749 }
1750
1751 return -EINVAL;
1752}
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764static int sdr_working_phase(struct socfpga_sdrseq *seq, const u32 grp,
1765 u32 *work_bgn, u32 *d, u32 *p, u32 *i)
1766{
1767 const u32 dtaps_per_ptap = seq->iocfg->delay_per_opa_tap /
1768 seq->iocfg->delay_per_dqs_en_dchain_tap;
1769 int ret;
1770
1771 *work_bgn = 0;
1772
1773 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1774 *i = 0;
1775 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, *d);
1776 ret = sdr_find_phase(seq, 1, grp, work_bgn, i, p);
1777 if (!ret)
1778 return 0;
1779 *work_bgn += seq->iocfg->delay_per_dqs_en_dchain_tap;
1780 }
1781
1782
1783 debug_cond(DLEVEL >= 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1784 __func__, __LINE__);
1785 return -EINVAL;
1786}
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796static void sdr_backup_phase(struct socfpga_sdrseq *seq, const u32 grp,
1797 u32 *work_bgn, u32 *p)
1798{
1799 u32 tmp_delay, d;
1800 int ret;
1801
1802
1803 if (*p == 0) {
1804 *p = seq->iocfg->dqs_en_phase_max;
1805 rw_mgr_decr_vfifo(seq, grp);
1806 } else {
1807 (*p)--;
1808 }
1809 tmp_delay = *work_bgn - seq->iocfg->delay_per_opa_tap;
1810 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *p);
1811
1812 for (d = 0; d <= seq->iocfg->dqs_en_delay_max && tmp_delay < *work_bgn;
1813 d++) {
1814 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, d);
1815
1816 ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
1817 PASS_ONE_BIT, 0);
1818 if (ret) {
1819 *work_bgn = tmp_delay;
1820 break;
1821 }
1822
1823 tmp_delay += seq->iocfg->delay_per_dqs_en_dchain_tap;
1824 }
1825
1826
1827 (*p)++;
1828 if (*p > seq->iocfg->dqs_en_phase_max) {
1829 *p = 0;
1830 rw_mgr_incr_vfifo(grp);
1831 }
1832
1833 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, 0);
1834}
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845static int sdr_nonworking_phase(struct socfpga_sdrseq *seq,
1846 const u32 grp, u32 *work_end, u32 *p, u32 *i)
1847{
1848 int ret;
1849
1850 (*p)++;
1851 *work_end += seq->iocfg->delay_per_opa_tap;
1852 if (*p > seq->iocfg->dqs_en_phase_max) {
1853
1854 *p = 0;
1855 rw_mgr_incr_vfifo(grp);
1856 }
1857
1858 ret = sdr_find_phase(seq, 0, grp, work_end, i, p);
1859 if (ret) {
1860
1861 debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n",
1862 __func__, __LINE__);
1863 }
1864
1865 return ret;
1866}
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876static int sdr_find_window_center(struct socfpga_sdrseq *seq,
1877 const u32 grp, const u32 work_bgn,
1878 const u32 work_end)
1879{
1880 u32 work_mid;
1881 int tmp_delay = 0;
1882 int i, p, d;
1883
1884 work_mid = (work_bgn + work_end) / 2;
1885
1886 debug_cond(DLEVEL >= 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1887 work_bgn, work_end, work_mid);
1888
1889 tmp_delay = (seq->iocfg->dqs_en_phase_max + 1)
1890 * seq->iocfg->delay_per_opa_tap;
1891
1892 debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay);
1893 work_mid %= tmp_delay;
1894 debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid);
1895
1896 tmp_delay = rounddown(work_mid, seq->iocfg->delay_per_opa_tap);
1897 if (tmp_delay > seq->iocfg->dqs_en_phase_max
1898 * seq->iocfg->delay_per_opa_tap) {
1899 tmp_delay = seq->iocfg->dqs_en_phase_max
1900 * seq->iocfg->delay_per_opa_tap;
1901 }
1902 p = tmp_delay / seq->iocfg->delay_per_opa_tap;
1903
1904 debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1905
1906 d = DIV_ROUND_UP(work_mid - tmp_delay,
1907 seq->iocfg->delay_per_dqs_en_dchain_tap);
1908 if (d > seq->iocfg->dqs_en_delay_max)
1909 d = seq->iocfg->dqs_en_delay_max;
1910 tmp_delay += d * seq->iocfg->delay_per_dqs_en_dchain_tap;
1911
1912 debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1913
1914 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
1915 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, d);
1916
1917
1918
1919
1920
1921 for (i = 0; i < seq->misccfg->read_valid_fifo_size; i++) {
1922 debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n");
1923 if (rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
1924 PASS_ONE_BIT,
1925 0)) {
1926 debug_cond(DLEVEL >= 2,
1927 "%s:%d center: found: ptap=%u dtap=%u\n",
1928 __func__, __LINE__, p, d);
1929 return 0;
1930 }
1931
1932
1933 rw_mgr_incr_vfifo(grp);
1934 }
1935
1936 debug_cond(DLEVEL >= 2, "%s:%d center: failed.\n",
1937 __func__, __LINE__);
1938 return -EINVAL;
1939}
1940
1941
1942
1943
1944
1945
1946
1947
1948static int
1949rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdrseq *seq,
1950 const u32 grp)
1951{
1952 u32 d, p, i;
1953 u32 dtaps_per_ptap;
1954 u32 work_bgn, work_end;
1955 u32 found_passing_read, found_failing_read = 0, initial_failing_dtap;
1956 int ret;
1957
1958 debug("%s:%d %u\n", __func__, __LINE__, grp);
1959
1960 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1961
1962 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, 0);
1963 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, 0);
1964
1965
1966 dtaps_per_ptap = seq->iocfg->delay_per_opa_tap /
1967 seq->iocfg->delay_per_dqs_en_dchain_tap;
1968
1969
1970 find_vfifo_failing_read(seq, grp);
1971
1972
1973 work_bgn = 0;
1974 ret = sdr_working_phase(seq, grp, &work_bgn, &d, &p, &i);
1975 if (ret)
1976 return ret;
1977
1978 work_end = work_bgn;
1979
1980
1981
1982
1983
1984
1985 if (d == 0) {
1986
1987
1988
1989
1990 sdr_backup_phase(seq, grp, &work_bgn, &p);
1991
1992
1993
1994
1995
1996 ret = sdr_nonworking_phase(seq, grp, &work_end, &p, &i);
1997 if (ret)
1998 return ret;
1999
2000
2001
2002
2003 if (p == 0) {
2004 p = seq->iocfg->dqs_en_phase_max;
2005 rw_mgr_decr_vfifo(seq, grp);
2006 } else {
2007 p = p - 1;
2008 }
2009
2010 work_end -= seq->iocfg->delay_per_opa_tap;
2011 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
2012
2013 d = 0;
2014
2015 debug_cond(DLEVEL >= 2, "%s:%d p: ptap=%u\n",
2016 __func__, __LINE__, p);
2017 }
2018
2019
2020 sdr_find_phase_delay(seq, 0, 1, grp, &work_end,
2021 seq->iocfg->delay_per_dqs_en_dchain_tap, &d);
2022
2023
2024 if (d != 0)
2025 work_end -= seq->iocfg->delay_per_dqs_en_dchain_tap;
2026
2027 debug_cond(DLEVEL >= 2,
2028 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
2029 __func__, __LINE__, p, d - 1, work_end);
2030
2031 if (work_end < work_bgn) {
2032
2033 debug_cond(DLEVEL >= 2, "%s:%d end-2: failed\n",
2034 __func__, __LINE__);
2035 return -EINVAL;
2036 }
2037
2038 debug_cond(DLEVEL >= 2, "%s:%d found range [%u,%u]\n",
2039 __func__, __LINE__, work_bgn, work_end);
2040
2041
2042
2043
2044
2045
2046 debug_cond(DLEVEL >= 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
2047 __func__, __LINE__);
2048
2049
2050 if (p == 0) {
2051 p = seq->iocfg->dqs_en_phase_max;
2052 rw_mgr_decr_vfifo(seq, grp);
2053 debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n",
2054 __func__, __LINE__, p);
2055 } else {
2056 p = p - 1;
2057 debug_cond(DLEVEL >= 2, "%s:%d backedup phase only: p=%u",
2058 __func__, __LINE__, p);
2059 }
2060
2061 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
2062
2063
2064
2065
2066
2067
2068
2069
2070 debug_cond(DLEVEL >= 2, "%s:%d find passing read\n",
2071 __func__, __LINE__);
2072
2073 initial_failing_dtap = d;
2074
2075 found_passing_read = !sdr_find_phase_delay(seq, 1, 1, grp, NULL, 0, &d);
2076 if (found_passing_read) {
2077
2078 debug_cond(DLEVEL >= 2, "%s:%d find failing read\n",
2079 __func__, __LINE__);
2080 d++;
2081 found_failing_read = !sdr_find_phase_delay(seq, 0, 1, grp, NULL,
2082 0, &d);
2083 } else {
2084 debug_cond(DLEVEL >= 1,
2085 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
2086 __func__, __LINE__);
2087 }
2088
2089
2090
2091
2092
2093
2094
2095 if (found_passing_read && found_failing_read)
2096 dtaps_per_ptap = d - initial_failing_dtap;
2097
2098 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
2099 debug_cond(DLEVEL >= 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
2100 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
2101
2102
2103 ret = sdr_find_window_center(seq, grp, work_bgn, work_end);
2104
2105 return ret;
2106}
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121static u32 search_stop_check(struct socfpga_sdrseq *seq, const int write,
2122 const int d, const int rank_bgn,
2123 const u32 write_group, const u32 read_group,
2124 u32 *bit_chk, u32 *sticky_bit_chk,
2125 const u32 use_read_test)
2126{
2127 const u32 ratio = seq->rwcfg->mem_if_read_dqs_width /
2128 seq->rwcfg->mem_if_write_dqs_width;
2129 const u32 correct_mask = write ? seq->param.write_correct_mask :
2130 seq->param.read_correct_mask;
2131 const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
2132 seq->rwcfg->mem_dq_per_read_dqs;
2133 u32 ret;
2134
2135
2136
2137
2138 if (write) {
2139 ret = !rw_mgr_mem_calibrate_write_test(seq, rank_bgn,
2140 write_group, 0,
2141 PASS_ONE_BIT, bit_chk,
2142 0);
2143 } else if (use_read_test) {
2144 ret = !rw_mgr_mem_calibrate_read_test(seq, rank_bgn, read_group,
2145 NUM_READ_PB_TESTS,
2146 PASS_ONE_BIT, bit_chk,
2147 0, 0);
2148 } else {
2149 rw_mgr_mem_calibrate_write_test(seq, rank_bgn, write_group, 0,
2150 PASS_ONE_BIT, bit_chk, 0);
2151 *bit_chk = *bit_chk >> (per_dqs *
2152 (read_group - (write_group * ratio)));
2153 ret = (*bit_chk == 0);
2154 }
2155 *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
2156 ret = ret && (*sticky_bit_chk == correct_mask);
2157 debug_cond(DLEVEL >= 2,
2158 "%s:%d center(left): dtap=%u => %u == %u && %u",
2159 __func__, __LINE__, d,
2160 *sticky_bit_chk, correct_mask, ret);
2161 return ret;
2162}
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178static void search_left_edge(struct socfpga_sdrseq *seq, const int write,
2179 const int rank_bgn, const u32 write_group,
2180 const u32 read_group, const u32 test_bgn,
2181 u32 *sticky_bit_chk, int *left_edge,
2182 int *right_edge, const u32 use_read_test)
2183{
2184 const u32 delay_max = write ? seq->iocfg->io_out1_delay_max :
2185 seq->iocfg->io_in_delay_max;
2186 const u32 dqs_max = write ? seq->iocfg->io_out1_delay_max :
2187 seq->iocfg->dqs_in_delay_max;
2188 const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
2189 seq->rwcfg->mem_dq_per_read_dqs;
2190 u32 stop, bit_chk;
2191 int i, d;
2192
2193 for (d = 0; d <= dqs_max; d++) {
2194 if (write)
2195 scc_mgr_apply_group_dq_out1_delay(seq, d);
2196 else
2197 scc_mgr_apply_group_dq_in_delay(seq, test_bgn, d);
2198
2199 writel(0, &sdr_scc_mgr->update);
2200
2201 stop = search_stop_check(seq, write, d, rank_bgn, write_group,
2202 read_group, &bit_chk, sticky_bit_chk,
2203 use_read_test);
2204 if (stop == 1)
2205 break;
2206
2207
2208 for (i = 0; i < per_dqs; i++) {
2209 if (bit_chk & 1) {
2210
2211
2212
2213
2214 left_edge[i] = d;
2215 } else {
2216
2217
2218
2219
2220
2221
2222 if (left_edge[i] == delay_max + 1)
2223 right_edge[i] = -(d + 1);
2224 }
2225 bit_chk >>= 1;
2226 }
2227 }
2228
2229
2230 if (write)
2231 scc_mgr_apply_group_dq_out1_delay(seq, 0);
2232 else
2233 scc_mgr_apply_group_dq_in_delay(seq, test_bgn, 0);
2234
2235 *sticky_bit_chk = 0;
2236 for (i = per_dqs - 1; i >= 0; i--) {
2237 debug_cond(DLEVEL >= 2,
2238 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
2239 __func__, __LINE__, i, left_edge[i],
2240 i, right_edge[i]);
2241
2242
2243
2244
2245
2246
2247 if ((left_edge[i] == delay_max + 1) &&
2248 (right_edge[i] != delay_max + 1)) {
2249 right_edge[i] = delay_max + 1;
2250 debug_cond(DLEVEL >= 2,
2251 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
2252 __func__, __LINE__, i, right_edge[i]);
2253 }
2254
2255
2256
2257
2258
2259
2260
2261
2262 *sticky_bit_chk <<= 1;
2263 if (write) {
2264 if (left_edge[i] != delay_max + 1)
2265 *sticky_bit_chk |= 1;
2266 } else {
2267 if ((left_edge[i] != delay_max + 1) &&
2268 (right_edge[i] != delay_max + 1))
2269 *sticky_bit_chk |= 1;
2270 }
2271 }
2272}
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289static int search_right_edge(struct socfpga_sdrseq *seq, const int write,
2290 const int rank_bgn, const u32 write_group,
2291 const u32 read_group, const int start_dqs,
2292 const int start_dqs_en, u32 *sticky_bit_chk,
2293 int *left_edge, int *right_edge,
2294 const u32 use_read_test)
2295{
2296 const u32 delay_max = write ? seq->iocfg->io_out1_delay_max :
2297 seq->iocfg->io_in_delay_max;
2298 const u32 dqs_max = write ? seq->iocfg->io_out1_delay_max :
2299 seq->iocfg->dqs_in_delay_max;
2300 const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
2301 seq->rwcfg->mem_dq_per_read_dqs;
2302 u32 stop, bit_chk;
2303 int i, d;
2304
2305 for (d = 0; d <= dqs_max - start_dqs; d++) {
2306 if (write) {
2307 scc_mgr_apply_group_dqs_io_and_oct_out1(seq,
2308 write_group,
2309 d + start_dqs);
2310 } else {
2311 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
2312 if (seq->iocfg->shift_dqs_en_when_shift_dqs) {
2313 u32 delay = d + start_dqs_en;
2314 if (delay > seq->iocfg->dqs_en_delay_max)
2315 delay = seq->iocfg->dqs_en_delay_max;
2316 scc_mgr_set_dqs_en_delay(read_group, delay);
2317 }
2318 scc_mgr_load_dqs(read_group);
2319 }
2320
2321 writel(0, &sdr_scc_mgr->update);
2322
2323 stop = search_stop_check(seq, write, d, rank_bgn, write_group,
2324 read_group, &bit_chk, sticky_bit_chk,
2325 use_read_test);
2326 if (stop == 1) {
2327 if (write && (d == 0)) {
2328 for (i = 0;
2329 i < seq->rwcfg->mem_dq_per_write_dqs;
2330 i++) {
2331
2332
2333
2334
2335
2336 if (right_edge[i] == delay_max + 1 &&
2337 left_edge[i] != delay_max + 1)
2338 right_edge[i] = -1;
2339 }
2340 }
2341 break;
2342 }
2343
2344
2345 for (i = 0; i < per_dqs; i++) {
2346 if (bit_chk & 1) {
2347
2348
2349
2350
2351 right_edge[i] = d;
2352 } else {
2353 if (d != 0) {
2354
2355
2356
2357
2358
2359
2360 if (right_edge[i] == delay_max + 1)
2361 left_edge[i] = -(d + 1);
2362 } else {
2363
2364
2365
2366
2367
2368
2369 if (right_edge[i] == delay_max + 1 &&
2370 left_edge[i] != delay_max + 1)
2371 right_edge[i] = -1;
2372
2373
2374
2375
2376
2377
2378 else if (right_edge[i] == delay_max + 1)
2379 left_edge[i] = -(d + 1);
2380 }
2381 }
2382
2383 debug_cond(DLEVEL >= 2, "%s:%d center[r,d=%u]: ",
2384 __func__, __LINE__, d);
2385 debug_cond(DLEVEL >= 2,
2386 "bit_chk_test=%i left_edge[%u]: %d ",
2387 bit_chk & 1, i, left_edge[i]);
2388 debug_cond(DLEVEL >= 2, "right_edge[%u]: %d\n", i,
2389 right_edge[i]);
2390 bit_chk >>= 1;
2391 }
2392 }
2393
2394
2395 for (i = 0; i < per_dqs; i++) {
2396 debug_cond(DLEVEL >= 2,
2397 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2398 __func__, __LINE__, i, left_edge[i],
2399 i, right_edge[i]);
2400 if ((left_edge[i] == dqs_max + 1) ||
2401 (right_edge[i] == dqs_max + 1))
2402 return i + 1;
2403 }
2404
2405 return 0;
2406}
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417static int get_window_mid_index(struct socfpga_sdrseq *seq,
2418 const int write, int *left_edge,
2419 int *right_edge, int *mid_min)
2420{
2421 const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
2422 seq->rwcfg->mem_dq_per_read_dqs;
2423 int i, mid, min_index;
2424
2425
2426 *mid_min = left_edge[0] - right_edge[0];
2427 min_index = 0;
2428 for (i = 1; i < per_dqs; i++) {
2429 mid = left_edge[i] - right_edge[i];
2430 if (mid < *mid_min) {
2431 *mid_min = mid;
2432 min_index = i;
2433 }
2434 }
2435
2436
2437
2438
2439
2440
2441
2442 if (*mid_min > 0)
2443 (*mid_min)++;
2444 *mid_min = *mid_min / 2;
2445
2446 debug_cond(DLEVEL >= 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
2447 __func__, __LINE__, *mid_min, min_index);
2448 return min_index;
2449}
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465static void center_dq_windows(struct socfpga_sdrseq *seq,
2466 const int write, int *left_edge, int *right_edge,
2467 const int mid_min, const int orig_mid_min,
2468 const int min_index, const int test_bgn,
2469 int *dq_margin, int *dqs_margin)
2470{
2471 const s32 delay_max = write ? seq->iocfg->io_out1_delay_max :
2472 seq->iocfg->io_in_delay_max;
2473 const s32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
2474 seq->rwcfg->mem_dq_per_read_dqs;
2475 const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
2476 SCC_MGR_IO_IN_DELAY_OFFSET;
2477 const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
2478
2479 s32 temp_dq_io_delay1;
2480 int shift_dq, i, p;
2481
2482
2483 *dqs_margin = delay_max + 1;
2484 *dq_margin = delay_max + 1;
2485
2486
2487 for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
2488
2489 shift_dq = (left_edge[i] - right_edge[i] -
2490 (left_edge[min_index] - right_edge[min_index]))/2 +
2491 (orig_mid_min - mid_min);
2492
2493 debug_cond(DLEVEL >= 2,
2494 "vfifo_center: before: shift_dq[%u]=%d\n",
2495 i, shift_dq);
2496
2497 temp_dq_io_delay1 = readl(addr + (i << 2));
2498
2499 if (shift_dq + temp_dq_io_delay1 > delay_max)
2500 shift_dq = delay_max - temp_dq_io_delay1;
2501 else if (shift_dq + temp_dq_io_delay1 < 0)
2502 shift_dq = -temp_dq_io_delay1;
2503
2504 debug_cond(DLEVEL >= 2,
2505 "vfifo_center: after: shift_dq[%u]=%d\n",
2506 i, shift_dq);
2507
2508 if (write)
2509 scc_mgr_set_dq_out1_delay(i,
2510 temp_dq_io_delay1 + shift_dq);
2511 else
2512 scc_mgr_set_dq_in_delay(p,
2513 temp_dq_io_delay1 + shift_dq);
2514
2515 scc_mgr_load_dq(p);
2516
2517 debug_cond(DLEVEL >= 2,
2518 "vfifo_center: margin[%u]=[%d,%d]\n", i,
2519 left_edge[i] - shift_dq + (-mid_min),
2520 right_edge[i] + shift_dq - (-mid_min));
2521
2522
2523 if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
2524 *dq_margin = left_edge[i] - shift_dq + (-mid_min);
2525
2526 if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
2527 *dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2528 }
2529}
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541static int rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdrseq *seq,
2542 const u32 rank_bgn,
2543 const u32 rw_group,
2544 const u32 test_bgn,
2545 const int use_read_test,
2546 const int update_fom)
2547{
2548 const u32 addr =
2549 SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
2550 (rw_group << 2);
2551
2552
2553
2554
2555 u32 sticky_bit_chk;
2556 s32 left_edge[seq->rwcfg->mem_dq_per_read_dqs];
2557 s32 right_edge[seq->rwcfg->mem_dq_per_read_dqs];
2558 s32 orig_mid_min, mid_min;
2559 s32 new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en;
2560 s32 dq_margin, dqs_margin;
2561 int i, min_index;
2562 int ret;
2563
2564 debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
2565
2566 start_dqs = readl(addr);
2567 if (seq->iocfg->shift_dqs_en_when_shift_dqs)
2568 start_dqs_en = readl(addr - seq->iocfg->dqs_en_delay_offset);
2569
2570
2571
2572 sticky_bit_chk = 0;
2573 for (i = 0; i < seq->rwcfg->mem_dq_per_read_dqs; i++) {
2574 left_edge[i] = seq->iocfg->io_in_delay_max + 1;
2575 right_edge[i] = seq->iocfg->io_in_delay_max + 1;
2576 }
2577
2578
2579 search_left_edge(seq, 0, rank_bgn, rw_group, rw_group, test_bgn,
2580 &sticky_bit_chk,
2581 left_edge, right_edge, use_read_test);
2582
2583
2584
2585 ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group,
2586 start_dqs, start_dqs_en,
2587 &sticky_bit_chk,
2588 left_edge, right_edge, use_read_test);
2589 if (ret) {
2590
2591
2592
2593
2594
2595 scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
2596 if (seq->iocfg->shift_dqs_en_when_shift_dqs)
2597 scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
2598
2599 scc_mgr_load_dqs(rw_group);
2600 writel(0, &sdr_scc_mgr->update);
2601
2602 debug_cond(DLEVEL >= 1,
2603 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2604 __func__, __LINE__, i, left_edge[i], right_edge[i]);
2605 if (use_read_test) {
2606 set_failing_group_stage(seq, rw_group *
2607 seq->rwcfg->mem_dq_per_read_dqs + i,
2608 CAL_STAGE_VFIFO,
2609 CAL_SUBSTAGE_VFIFO_CENTER);
2610 } else {
2611 set_failing_group_stage(seq, rw_group *
2612 seq->rwcfg->mem_dq_per_read_dqs + i,
2613 CAL_STAGE_VFIFO_AFTER_WRITES,
2614 CAL_SUBSTAGE_VFIFO_CENTER);
2615 }
2616 return -EIO;
2617 }
2618
2619 min_index = get_window_mid_index(seq, 0, left_edge, right_edge,
2620 &mid_min);
2621
2622
2623 orig_mid_min = mid_min;
2624 new_dqs = start_dqs - mid_min;
2625 if (new_dqs > seq->iocfg->dqs_in_delay_max)
2626 new_dqs = seq->iocfg->dqs_in_delay_max;
2627 else if (new_dqs < 0)
2628 new_dqs = 0;
2629
2630 mid_min = start_dqs - new_dqs;
2631 debug_cond(DLEVEL >= 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2632 mid_min, new_dqs);
2633
2634 if (seq->iocfg->shift_dqs_en_when_shift_dqs) {
2635 if (start_dqs_en - mid_min > seq->iocfg->dqs_en_delay_max)
2636 mid_min += start_dqs_en - mid_min -
2637 seq->iocfg->dqs_en_delay_max;
2638 else if (start_dqs_en - mid_min < 0)
2639 mid_min += start_dqs_en - mid_min;
2640 }
2641 new_dqs = start_dqs - mid_min;
2642
2643 debug_cond(DLEVEL >= 1,
2644 "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
2645 start_dqs,
2646 seq->iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
2647 new_dqs, mid_min);
2648
2649
2650 center_dq_windows(seq, 0, left_edge, right_edge, mid_min, orig_mid_min,
2651 min_index, test_bgn, &dq_margin, &dqs_margin);
2652
2653
2654 if (seq->iocfg->shift_dqs_en_when_shift_dqs) {
2655 final_dqs_en = start_dqs_en - mid_min;
2656 scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
2657 scc_mgr_load_dqs(rw_group);
2658 }
2659
2660
2661 scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
2662 scc_mgr_load_dqs(rw_group);
2663 debug_cond(DLEVEL >= 2,
2664 "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
2665 __func__, __LINE__, dq_margin, dqs_margin);
2666
2667
2668
2669
2670
2671 writel(0, &sdr_scc_mgr->update);
2672
2673 if ((dq_margin < 0) || (dqs_margin < 0))
2674 return -EINVAL;
2675
2676 return 0;
2677}
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689static int rw_mgr_mem_calibrate_guaranteed_write(struct socfpga_sdrseq *seq,
2690 const u32 rw_group,
2691 const u32 phase)
2692{
2693 int ret;
2694
2695
2696 scc_mgr_set_dqdqs_output_phase_all_ranks(seq, rw_group, phase);
2697
2698 debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n",
2699 __func__, __LINE__, rw_group, phase);
2700
2701
2702
2703
2704
2705
2706 rw_mgr_mem_calibrate_read_load_patterns(seq, 0, 1);
2707
2708 if (seq->gbl.phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2709 return 0;
2710
2711
2712
2713
2714
2715 ret = rw_mgr_mem_calibrate_read_test_patterns(seq, 0, rw_group, 1);
2716 if (ret)
2717 debug_cond(DLEVEL >= 1,
2718 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2719 __func__, __LINE__, rw_group, phase);
2720 return ret;
2721}
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731static int
2732rw_mgr_mem_calibrate_dqs_enable_calibration(struct socfpga_sdrseq *seq,
2733 const u32 rw_group,
2734 const u32 test_bgn)
2735{
2736
2737
2738
2739
2740
2741
2742 const u32 delay_step = seq->iocfg->io_in_delay_max /
2743 (seq->rwcfg->mem_dq_per_read_dqs - 1);
2744 int ret;
2745 u32 i, p, d, r;
2746
2747 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2748
2749
2750 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
2751 r += NUM_RANKS_PER_SHADOW_REG) {
2752 for (i = 0, p = test_bgn, d = 0;
2753 i < seq->rwcfg->mem_dq_per_read_dqs;
2754 i++, p++, d += delay_step) {
2755 debug_cond(DLEVEL >= 1,
2756 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2757 __func__, __LINE__, rw_group, r, i, p, d);
2758
2759 scc_mgr_set_dq_in_delay(p, d);
2760 scc_mgr_load_dq(p);
2761 }
2762
2763 writel(0, &sdr_scc_mgr->update);
2764 }
2765
2766
2767
2768
2769
2770 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(seq, rw_group);
2771
2772 debug_cond(DLEVEL >= 1,
2773 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2774 __func__, __LINE__, rw_group, !ret);
2775
2776 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
2777 r += NUM_RANKS_PER_SHADOW_REG) {
2778 scc_mgr_apply_group_dq_in_delay(seq, test_bgn, 0);
2779 writel(0, &sdr_scc_mgr->update);
2780 }
2781
2782 return ret;
2783}
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795static int
2796rw_mgr_mem_calibrate_dq_dqs_centering(struct socfpga_sdrseq *seq,
2797 const u32 rw_group, const u32 test_bgn,
2798 const int use_read_test,
2799 const int update_fom)
2800
2801{
2802 int ret, grp_calibrated;
2803 u32 rank_bgn, sr;
2804
2805
2806
2807
2808
2809 grp_calibrated = 1;
2810 for (rank_bgn = 0, sr = 0;
2811 rank_bgn < seq->rwcfg->mem_number_of_ranks;
2812 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2813 ret = rw_mgr_mem_calibrate_vfifo_center(seq, rank_bgn, rw_group,
2814 test_bgn,
2815 use_read_test,
2816 update_fom);
2817 if (!ret)
2818 continue;
2819
2820 grp_calibrated = 0;
2821 }
2822
2823 if (!grp_calibrated)
2824 return -EIO;
2825
2826 return 0;
2827}
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844static int rw_mgr_mem_calibrate_vfifo(struct socfpga_sdrseq *seq,
2845 const u32 rw_group, const u32 test_bgn)
2846{
2847 u32 p, d;
2848 u32 dtaps_per_ptap;
2849 u32 failed_substage;
2850
2851 int ret;
2852
2853 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2854
2855
2856 reg_file_set_group(rw_group);
2857 reg_file_set_stage(CAL_STAGE_VFIFO);
2858 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2859
2860 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2861
2862
2863 dtaps_per_ptap = DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap,
2864 seq->iocfg->delay_per_dqs_en_dchain_tap)
2865 - 1;
2866
2867 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2868
2869
2870
2871
2872
2873
2874 if (d > 0) {
2875 scc_mgr_apply_group_all_out_delay_add_all_ranks(seq,
2876 rw_group,
2877 d);
2878 }
2879
2880 for (p = 0; p <= seq->iocfg->dqdqs_out_phase_max; p++) {
2881
2882 ret = rw_mgr_mem_calibrate_guaranteed_write(seq,
2883 rw_group,
2884 p);
2885 if (ret)
2886 break;
2887
2888
2889 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(seq,
2890 rw_group,
2891 test_bgn);
2892 if (ret) {
2893 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2894 continue;
2895 }
2896
2897
2898
2899
2900
2901
2902 ret = rw_mgr_mem_calibrate_dq_dqs_centering(seq,
2903 rw_group,
2904 test_bgn,
2905 1, 0);
2906 if (ret) {
2907 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2908 continue;
2909 }
2910
2911
2912 goto cal_done_ok;
2913 }
2914 }
2915
2916
2917 set_failing_group_stage(seq, rw_group, CAL_STAGE_VFIFO,
2918 failed_substage);
2919 return 0;
2920
2921
2922cal_done_ok:
2923
2924
2925
2926
2927
2928 if (d > 2)
2929 scc_mgr_zero_group(seq, rw_group, 1);
2930
2931 return 1;
2932}
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944static int rw_mgr_mem_calibrate_vfifo_end(struct socfpga_sdrseq *seq,
2945 const u32 rw_group,
2946 const u32 test_bgn)
2947{
2948 int ret;
2949
2950 debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn);
2951
2952
2953 reg_file_set_group(rw_group);
2954 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2955 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2956
2957 ret = rw_mgr_mem_calibrate_dq_dqs_centering(seq, rw_group, test_bgn, 0,
2958 1);
2959 if (ret)
2960 set_failing_group_stage(seq, rw_group,
2961 CAL_STAGE_VFIFO_AFTER_WRITES,
2962 CAL_SUBSTAGE_VFIFO_CENTER);
2963 return ret;
2964}
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975static u32 rw_mgr_mem_calibrate_lfifo(struct socfpga_sdrseq *seq)
2976{
2977 int found_one = 0;
2978
2979 debug("%s:%d\n", __func__, __LINE__);
2980
2981
2982 reg_file_set_stage(CAL_STAGE_LFIFO);
2983 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2984
2985
2986 rw_mgr_mem_calibrate_read_load_patterns(seq, 0, 1);
2987
2988 do {
2989 writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
2990 debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u",
2991 __func__, __LINE__, seq->gbl.curr_read_lat);
2992
2993 if (!rw_mgr_mem_calibrate_read_test_all_ranks(seq, 0,
2994 NUM_READ_TESTS,
2995 PASS_ALL_BITS, 1))
2996 break;
2997
2998 found_one = 1;
2999
3000
3001
3002
3003 seq->gbl.curr_read_lat--;
3004 } while (seq->gbl.curr_read_lat > 0);
3005
3006
3007 writel(0, &phy_mgr_cmd->fifo_reset);
3008
3009 if (found_one) {
3010
3011 seq->gbl.curr_read_lat += 2;
3012 writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
3013 debug_cond(DLEVEL >= 2,
3014 "%s:%d lfifo: success: using read_lat=%u\n",
3015 __func__, __LINE__, seq->gbl.curr_read_lat);
3016 } else {
3017 set_failing_group_stage(seq, 0xff, CAL_STAGE_LFIFO,
3018 CAL_SUBSTAGE_READ_LATENCY);
3019
3020 debug_cond(DLEVEL >= 2,
3021 "%s:%d lfifo: failed at initial read_lat=%u\n",
3022 __func__, __LINE__, seq->gbl.curr_read_lat);
3023 }
3024
3025 return found_one;
3026}
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043static void search_window(struct socfpga_sdrseq *seq,
3044 const int search_dm, const u32 rank_bgn,
3045 const u32 write_group, int *bgn_curr, int *end_curr,
3046 int *bgn_best, int *end_best, int *win_best,
3047 int new_dqs)
3048{
3049 u32 bit_chk;
3050 const int max = seq->iocfg->io_out1_delay_max - new_dqs;
3051 int d, di;
3052
3053
3054 for (di = max; di >= 0; di -= DELTA_D) {
3055 if (search_dm) {
3056 d = di;
3057 scc_mgr_apply_group_dm_out1_delay(seq, d);
3058 } else {
3059
3060 d = max - di;
3061
3062
3063
3064
3065 scc_mgr_apply_group_dqs_io_and_oct_out1(seq,
3066 write_group,
3067 d + new_dqs);
3068 }
3069
3070 writel(0, &sdr_scc_mgr->update);
3071
3072 if (rw_mgr_mem_calibrate_write_test(seq, rank_bgn, write_group,
3073 1, PASS_ALL_BITS, &bit_chk,
3074 0)) {
3075
3076 *end_curr = search_dm ? -d : d;
3077
3078
3079
3080
3081
3082 if (*bgn_curr == seq->iocfg->io_out1_delay_max + 1)
3083 *bgn_curr = search_dm ? -d : d;
3084
3085
3086
3087
3088
3089 if ((*end_curr - *bgn_curr + 1) > *win_best) {
3090 *win_best = *end_curr - *bgn_curr + 1;
3091 *bgn_best = *bgn_curr;
3092 *end_best = *end_curr;
3093 }
3094 } else {
3095
3096 *bgn_curr = seq->iocfg->io_out1_delay_max + 1;
3097 *end_curr = seq->iocfg->io_out1_delay_max + 1;
3098
3099
3100 if (search_dm)
3101 continue;
3102
3103
3104
3105
3106
3107
3108 if (*win_best - 1 > seq->iocfg->io_out1_delay_max
3109 - new_dqs - d)
3110 break;
3111 }
3112 }
3113}
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124static int
3125rw_mgr_mem_calibrate_writes_center(struct socfpga_sdrseq *seq,
3126 const u32 rank_bgn, const u32 write_group,
3127 const u32 test_bgn)
3128{
3129 int i;
3130 u32 sticky_bit_chk;
3131 u32 min_index;
3132 int left_edge[seq->rwcfg->mem_dq_per_write_dqs];
3133 int right_edge[seq->rwcfg->mem_dq_per_write_dqs];
3134 int mid;
3135 int mid_min, orig_mid_min;
3136 int new_dqs, start_dqs;
3137 int dq_margin, dqs_margin, dm_margin;
3138 int bgn_curr = seq->iocfg->io_out1_delay_max + 1;
3139 int end_curr = seq->iocfg->io_out1_delay_max + 1;
3140 int bgn_best = seq->iocfg->io_out1_delay_max + 1;
3141 int end_best = seq->iocfg->io_out1_delay_max + 1;
3142 int win_best = 0;
3143
3144 int ret;
3145
3146 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
3147
3148 dm_margin = 0;
3149
3150 start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
3151 SCC_MGR_IO_OUT1_DELAY_OFFSET) +
3152 (seq->rwcfg->mem_dq_per_write_dqs << 2));
3153
3154
3155
3156
3157
3158
3159
3160 sticky_bit_chk = 0;
3161 for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) {
3162 left_edge[i] = seq->iocfg->io_out1_delay_max + 1;
3163 right_edge[i] = seq->iocfg->io_out1_delay_max + 1;
3164 }
3165
3166
3167 search_left_edge(seq, 1, rank_bgn, write_group, 0, test_bgn,
3168 &sticky_bit_chk,
3169 left_edge, right_edge, 0);
3170
3171
3172 ret = search_right_edge(seq, 1, rank_bgn, write_group, 0,
3173 start_dqs, 0,
3174 &sticky_bit_chk,
3175 left_edge, right_edge, 0);
3176 if (ret) {
3177 set_failing_group_stage(seq, test_bgn + ret - 1,
3178 CAL_STAGE_WRITES,
3179 CAL_SUBSTAGE_WRITES_CENTER);
3180 return -EINVAL;
3181 }
3182
3183 min_index = get_window_mid_index(seq, 1, left_edge, right_edge,
3184 &mid_min);
3185
3186
3187 orig_mid_min = mid_min;
3188 new_dqs = start_dqs;
3189 mid_min = 0;
3190 debug_cond(DLEVEL >= 1,
3191 "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
3192 __func__, __LINE__, start_dqs, new_dqs, mid_min);
3193
3194
3195 center_dq_windows(seq, 1, left_edge, right_edge, mid_min, orig_mid_min,
3196 min_index, 0, &dq_margin, &dqs_margin);
3197
3198
3199 scc_mgr_apply_group_dqs_io_and_oct_out1(seq, write_group, new_dqs);
3200 writel(0, &sdr_scc_mgr->update);
3201
3202
3203 debug_cond(DLEVEL >= 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3204
3205
3206
3207
3208
3209 left_edge[0] = seq->iocfg->io_out1_delay_max + 1;
3210 right_edge[0] = seq->iocfg->io_out1_delay_max + 1;
3211
3212
3213 search_window(seq, 1, rank_bgn, write_group, &bgn_curr, &end_curr,
3214 &bgn_best, &end_best, &win_best, 0);
3215
3216
3217 scc_mgr_apply_group_dm_out1_delay(seq, 0);
3218
3219
3220
3221
3222
3223
3224 if (end_curr != 0) {
3225 bgn_curr = seq->iocfg->io_out1_delay_max + 1;
3226 end_curr = seq->iocfg->io_out1_delay_max + 1;
3227 }
3228
3229
3230 search_window(seq, 0, rank_bgn, write_group, &bgn_curr, &end_curr,
3231 &bgn_best, &end_best, &win_best, new_dqs);
3232
3233
3234 left_edge[0] = -1 * bgn_best;
3235 right_edge[0] = end_best;
3236
3237 debug_cond(DLEVEL >= 2, "%s:%d dm_calib: left=%d right=%d\n",
3238 __func__, __LINE__, left_edge[0], right_edge[0]);
3239
3240
3241 scc_mgr_apply_group_dqs_io_and_oct_out1(seq, write_group, new_dqs);
3242
3243
3244
3245
3246 mid = (left_edge[0] - right_edge[0]) / 2;
3247
3248
3249 if (mid < 0)
3250 mid = 0;
3251
3252
3253 if (win_best == 0)
3254 dm_margin = -1;
3255 else
3256 dm_margin = left_edge[0] - mid;
3257
3258 scc_mgr_apply_group_dm_out1_delay(seq, mid);
3259 writel(0, &sdr_scc_mgr->update);
3260
3261 debug_cond(DLEVEL >= 2,
3262 "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
3263 __func__, __LINE__, left_edge[0], right_edge[0],
3264 mid, dm_margin);
3265
3266 seq->gbl.fom_out += dq_margin + dqs_margin;
3267
3268 debug_cond(DLEVEL >= 2,
3269 "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
3270 __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
3271
3272
3273
3274
3275
3276 writel(0, &sdr_scc_mgr->update);
3277
3278 if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0))
3279 return -EINVAL;
3280
3281 return 0;
3282}
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295static int rw_mgr_mem_calibrate_writes(struct socfpga_sdrseq *seq,
3296 const u32 rank_bgn, const u32 group,
3297 const u32 test_bgn)
3298{
3299 int ret;
3300
3301
3302 debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
3303
3304 reg_file_set_group(group);
3305 reg_file_set_stage(CAL_STAGE_WRITES);
3306 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3307
3308 ret = rw_mgr_mem_calibrate_writes_center(seq, rank_bgn, group,
3309 test_bgn);
3310 if (ret)
3311 set_failing_group_stage(seq, group, CAL_STAGE_WRITES,
3312 CAL_SUBSTAGE_WRITES_CENTER);
3313
3314 return ret;
3315}
3316
3317
3318
3319
3320
3321
3322static void mem_precharge_and_activate(struct socfpga_sdrseq *seq)
3323{
3324 int r;
3325
3326 for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) {
3327
3328 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF);
3329
3330
3331 writel(seq->rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3332 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3333
3334 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3335 writel(seq->rwcfg->activate_0_and_1_wait1,
3336 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3337
3338 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3339 writel(seq->rwcfg->activate_0_and_1_wait2,
3340 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3341
3342
3343 writel(seq->rwcfg->activate_0_and_1,
3344 SDR_PHYGRP_RWMGRGRP_ADDRESS |
3345 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3346 }
3347}
3348
3349
3350
3351
3352
3353
3354static void mem_init_latency(struct socfpga_sdrseq *seq)
3355{
3356
3357
3358
3359
3360
3361 const u32 max_latency = (1 << seq->misccfg->max_latency_count_width)
3362 - 1;
3363 u32 rlat, wlat;
3364
3365 debug("%s:%d\n", __func__, __LINE__);
3366
3367
3368
3369
3370
3371 wlat = readl(&data_mgr->t_wl_add);
3372 wlat += readl(&data_mgr->mem_t_add);
3373
3374 seq->gbl.rw_wl_nop_cycles = wlat - 1;
3375
3376
3377 rlat = readl(&data_mgr->t_rl_add);
3378
3379
3380 seq->gbl.curr_read_lat = rlat + 16;
3381 if (seq->gbl.curr_read_lat > max_latency)
3382 seq->gbl.curr_read_lat = max_latency;
3383
3384 writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
3385
3386
3387 writel(wlat, &phy_mgr_cfg->afi_wlat);
3388}
3389
3390
3391
3392
3393
3394
3395static void mem_skip_calibrate(struct socfpga_sdrseq *seq)
3396{
3397 u32 vfifo_offset;
3398 u32 i, j, r;
3399
3400 debug("%s:%d\n", __func__, __LINE__);
3401
3402 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
3403 r += NUM_RANKS_PER_SHADOW_REG) {
3404
3405
3406
3407
3408 for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
3409 scc_mgr_set_dqs_en_phase(i, 0);
3410 if (seq->iocfg->dll_chain_length == 6)
3411 scc_mgr_set_dqdqs_output_phase(i, 6);
3412 else
3413 scc_mgr_set_dqdqs_output_phase(i, 7);
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441 scc_mgr_set_dqdqs_output_phase(i,
3442 ((125 * seq->iocfg->dll_chain_length)
3443 / 100) - 2);
3444 }
3445 writel(0xff, &sdr_scc_mgr->dqs_ena);
3446 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3447
3448 for (i = 0; i < seq->rwcfg->mem_if_write_dqs_width; i++) {
3449 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3450 SCC_MGR_GROUP_COUNTER_OFFSET);
3451 }
3452 writel(0xff, &sdr_scc_mgr->dq_ena);
3453 writel(0xff, &sdr_scc_mgr->dm_ena);
3454 writel(0, &sdr_scc_mgr->update);
3455 }
3456
3457
3458 for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
3459 scc_mgr_set_dqs_bus_in_delay(i, 10);
3460 scc_mgr_load_dqs(i);
3461 }
3462 writel(0, &sdr_scc_mgr->update);
3463
3464
3465
3466
3467
3468 vfifo_offset = seq->misccfg->calib_vfifo_offset;
3469 for (j = 0; j < vfifo_offset; j++)
3470 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3471 writel(0, &phy_mgr_cmd->fifo_reset);
3472
3473
3474
3475
3476
3477 seq->gbl.curr_read_lat = seq->misccfg->calib_lfifo_offset;
3478 writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
3479}
3480
3481
3482
3483
3484
3485
3486static u32 mem_calibrate(struct socfpga_sdrseq *seq)
3487{
3488 u32 i;
3489 u32 rank_bgn, sr;
3490 u32 write_group, write_test_bgn;
3491 u32 read_group, read_test_bgn;
3492 u32 run_groups, current_run;
3493 u32 failing_groups = 0;
3494 u32 group_failed = 0;
3495
3496 const u32 rwdqs_ratio = seq->rwcfg->mem_if_read_dqs_width /
3497 seq->rwcfg->mem_if_write_dqs_width;
3498
3499 debug("%s:%d\n", __func__, __LINE__);
3500
3501
3502 seq->gbl.error_substage = CAL_SUBSTAGE_NIL;
3503 seq->gbl.error_stage = CAL_STAGE_NIL;
3504 seq->gbl.error_group = 0xff;
3505 seq->gbl.fom_in = 0;
3506 seq->gbl.fom_out = 0;
3507
3508
3509 mem_init_latency(seq);
3510
3511
3512 mem_precharge_and_activate(seq);
3513
3514 for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
3515 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3516 SCC_MGR_GROUP_COUNTER_OFFSET);
3517
3518 if (i == 0)
3519 scc_mgr_set_hhp_extras();
3520
3521 scc_set_bypass_mode(i);
3522 }
3523
3524
3525 if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3526
3527
3528
3529
3530 mem_skip_calibrate(seq);
3531
3532
3533
3534
3535
3536 writel(0, &sdr_scc_mgr->update);
3537 return 1;
3538 }
3539
3540
3541 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3542
3543
3544
3545
3546 scc_mgr_zero_all(seq);
3547
3548 run_groups = ~0;
3549
3550 for (write_group = 0, write_test_bgn = 0; write_group
3551 < seq->rwcfg->mem_if_write_dqs_width; write_group++,
3552 write_test_bgn += seq->rwcfg->mem_dq_per_write_dqs) {
3553
3554 group_failed = 0;
3555
3556 current_run = run_groups & ((1 <<
3557 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3558 run_groups = run_groups >>
3559 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3560
3561 if (current_run == 0)
3562 continue;
3563
3564 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3565 SCC_MGR_GROUP_COUNTER_OFFSET);
3566 scc_mgr_zero_group(seq, write_group, 0);
3567
3568 for (read_group = write_group * rwdqs_ratio,
3569 read_test_bgn = 0;
3570 read_group < (write_group + 1) * rwdqs_ratio;
3571 read_group++,
3572 read_test_bgn += seq->rwcfg->mem_dq_per_read_dqs) {
3573 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3574 continue;
3575
3576
3577 if (rw_mgr_mem_calibrate_vfifo(seq, read_group,
3578 read_test_bgn))
3579 continue;
3580
3581 if (!(seq->gbl.phy_debug_mode_flags &
3582 PHY_DEBUG_SWEEP_ALL_GROUPS))
3583 return 0;
3584
3585
3586 goto grp_failed;
3587 }
3588
3589
3590 for (rank_bgn = 0, sr = 0;
3591 rank_bgn < seq->rwcfg->mem_number_of_ranks;
3592 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3593 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3594 continue;
3595
3596
3597 if (STATIC_CALIB_STEPS &
3598 CALIB_SKIP_DELAY_SWEEPS)
3599 continue;
3600
3601
3602 if (!rw_mgr_mem_calibrate_writes(seq, rank_bgn,
3603 write_group,
3604 write_test_bgn))
3605 continue;
3606
3607 group_failed = 1;
3608 if (!(seq->gbl.phy_debug_mode_flags &
3609 PHY_DEBUG_SWEEP_ALL_GROUPS))
3610 return 0;
3611 }
3612
3613
3614 if (group_failed)
3615 goto grp_failed;
3616
3617 for (read_group = write_group * rwdqs_ratio,
3618 read_test_bgn = 0;
3619 read_group < (write_group + 1) * rwdqs_ratio;
3620 read_group++,
3621 read_test_bgn += seq->rwcfg->mem_dq_per_read_dqs) {
3622 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3623 continue;
3624
3625 if (!rw_mgr_mem_calibrate_vfifo_end(seq,
3626 read_group,
3627 read_test_bgn))
3628 continue;
3629
3630 if (!(seq->gbl.phy_debug_mode_flags &
3631 PHY_DEBUG_SWEEP_ALL_GROUPS))
3632 return 0;
3633
3634
3635 goto grp_failed;
3636 }
3637
3638
3639 continue;
3640
3641grp_failed:
3642 failing_groups++;
3643 }
3644
3645
3646
3647
3648
3649 if (failing_groups != 0)
3650 return 0;
3651
3652 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3653 continue;
3654
3655
3656 if (!rw_mgr_mem_calibrate_lfifo(seq))
3657 return 0;
3658 }
3659
3660
3661
3662
3663
3664 writel(0, &sdr_scc_mgr->update);
3665 return 1;
3666}
3667
3668
3669
3670
3671
3672
3673static int run_mem_calibrate(struct socfpga_sdrseq *seq)
3674{
3675 int pass;
3676 u32 ctrl_cfg;
3677
3678 debug("%s:%d\n", __func__, __LINE__);
3679
3680
3681 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3682
3683
3684 ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg);
3685 writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
3686 &sdr_ctrl->ctrl_cfg);
3687
3688 phy_mgr_initialize(seq);
3689 rw_mgr_mem_initialize(seq);
3690
3691
3692 pass = mem_calibrate(seq);
3693
3694 mem_precharge_and_activate(seq);
3695 writel(0, &phy_mgr_cmd->fifo_reset);
3696
3697
3698 rw_mgr_mem_handoff(seq);
3699
3700
3701
3702
3703
3704 writel(0x2, &phy_mgr_cfg->mux_sel);
3705
3706
3707 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
3708
3709 return pass;
3710}
3711
3712
3713
3714
3715
3716
3717
3718
3719static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass)
3720{
3721 u32 debug_info;
3722
3723 if (pass) {
3724 debug("%s: CALIBRATION PASSED\n", __FILE__);
3725
3726 seq->gbl.fom_in /= 2;
3727 seq->gbl.fom_out /= 2;
3728
3729 if (seq->gbl.fom_in > 0xff)
3730 seq->gbl.fom_in = 0xff;
3731
3732 if (seq->gbl.fom_out > 0xff)
3733 seq->gbl.fom_out = 0xff;
3734
3735
3736 debug_info = seq->gbl.fom_in;
3737 debug_info |= seq->gbl.fom_out << 8;
3738 writel(debug_info, &sdr_reg_file->fom);
3739
3740 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3741 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3742 } else {
3743 debug("%s: CALIBRATION FAILED\n", __FILE__);
3744
3745 debug_info = seq->gbl.error_stage;
3746 debug_info |= seq->gbl.error_substage << 8;
3747 debug_info |= seq->gbl.error_group << 16;
3748
3749 writel(debug_info, &sdr_reg_file->failing_stage);
3750 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3751 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3752
3753
3754 debug_info = seq->gbl.error_stage;
3755 debug_info |= seq->gbl.error_substage << 8;
3756 debug_info |= seq->gbl.error_group << 16;
3757 writel(debug_info, &sdr_reg_file->failing_stage);
3758 }
3759
3760 debug("%s: Calibration complete\n", __FILE__);
3761}
3762
3763
3764
3765
3766
3767
3768static void hc_initialize_rom_data(void)
3769{
3770 unsigned int nelem = 0;
3771 const u32 *rom_init;
3772 u32 i, addr;
3773
3774 socfpga_get_seq_inst_init(&rom_init, &nelem);
3775 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3776 for (i = 0; i < nelem; i++)
3777 writel(rom_init[i], addr + (i << 2));
3778
3779 socfpga_get_seq_ac_init(&rom_init, &nelem);
3780 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3781 for (i = 0; i < nelem; i++)
3782 writel(rom_init[i], addr + (i << 2));
3783}
3784
3785
3786
3787
3788
3789
3790static void initialize_reg_file(struct socfpga_sdrseq *seq)
3791{
3792
3793 writel(seq->misccfg->reg_file_init_seq_signature,
3794 &sdr_reg_file->signature);
3795 writel(0, &sdr_reg_file->debug_data_addr);
3796 writel(0, &sdr_reg_file->cur_stage);
3797 writel(0, &sdr_reg_file->fom);
3798 writel(0, &sdr_reg_file->failing_stage);
3799 writel(0, &sdr_reg_file->debug1);
3800 writel(0, &sdr_reg_file->debug2);
3801}
3802
3803
3804
3805
3806
3807
3808static void initialize_hps_phy(void)
3809{
3810 u32 reg;
3811
3812
3813
3814
3815 u32 trk_sample_count = 7500;
3816 u32 trk_long_idle_sample_count = (10 << 16) | 100;
3817
3818
3819
3820
3821
3822 reg = 0;
3823 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3824 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3825 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3826 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3827 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3828 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3829
3830
3831
3832
3833 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3834 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3835 trk_sample_count);
3836 writel(reg, &sdr_ctrl->phy_ctrl0);
3837
3838 reg = 0;
3839 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3840 trk_sample_count >>
3841 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3842 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3843 trk_long_idle_sample_count);
3844 writel(reg, &sdr_ctrl->phy_ctrl1);
3845
3846 reg = 0;
3847 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3848 trk_long_idle_sample_count >>
3849 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3850 writel(reg, &sdr_ctrl->phy_ctrl2);
3851}
3852
3853
3854
3855
3856
3857
3858static void initialize_tracking(struct socfpga_sdrseq *seq)
3859{
3860
3861
3862
3863
3864
3865 writel(DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap,
3866 seq->iocfg->delay_per_dchain_tap) - 1,
3867 &sdr_reg_file->dtaps_per_ptap);
3868
3869
3870 writel(7500, &sdr_reg_file->trk_sample_count);
3871
3872
3873 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3874
3875
3876
3877
3878
3879
3880
3881 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3882 &sdr_reg_file->delays);
3883
3884
3885 if (dram_is_ddr(2)) {
3886 writel(0, &sdr_reg_file->trk_rw_mgr_addr);
3887 } else if (dram_is_ddr(3)) {
3888 writel((seq->rwcfg->idle << 24) |
3889 (seq->rwcfg->activate_1 << 16) |
3890 (seq->rwcfg->sgle_read << 8) |
3891 (seq->rwcfg->precharge_all << 0),
3892 &sdr_reg_file->trk_rw_mgr_addr);
3893 }
3894
3895 writel(seq->rwcfg->mem_if_read_dqs_width,
3896 &sdr_reg_file->trk_read_dqs_width);
3897
3898
3899 if (dram_is_ddr(2)) {
3900 writel(1000 << 0, &sdr_reg_file->trk_rfsh);
3901 } else if (dram_is_ddr(3)) {
3902 writel((seq->rwcfg->refresh_all << 24) | (1000 << 0),
3903 &sdr_reg_file->trk_rfsh);
3904 }
3905}
3906
3907int sdram_calibration_full(struct socfpga_sdr *sdr)
3908{
3909 u32 pass;
3910 struct socfpga_sdrseq seq;
3911
3912
3913
3914
3915
3916 if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS)
3917 return -ENODEV;
3918
3919 memset(&seq, 0, sizeof(seq));
3920
3921 seq.rwcfg = socfpga_get_sdram_rwmgr_config();
3922 seq.iocfg = socfpga_get_sdram_io_config();
3923 seq.misccfg = socfpga_get_sdram_misc_config();
3924
3925
3926 seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3927
3928
3929
3930
3931#if DISABLE_GUARANTEED_READ
3932 seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3933#endif
3934
3935 initialize_reg_file(&seq);
3936
3937
3938 initialize_hps_phy();
3939
3940 scc_mgr_initialize();
3941
3942 initialize_tracking(&seq);
3943
3944 debug("%s: Preparing to start memory calibration\n", __FILE__);
3945
3946 debug("%s:%d\n", __func__, __LINE__);
3947 debug_cond(DLEVEL >= 1,
3948 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3949 seq.rwcfg->mem_number_of_ranks,
3950 seq.rwcfg->mem_number_of_cs_per_dimm,
3951 seq.rwcfg->mem_dq_per_read_dqs,
3952 seq.rwcfg->mem_dq_per_write_dqs,
3953 seq.rwcfg->mem_virtual_groups_per_read_dqs,
3954 seq.rwcfg->mem_virtual_groups_per_write_dqs);
3955 debug_cond(DLEVEL >= 1,
3956 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3957 seq.rwcfg->mem_if_read_dqs_width,
3958 seq.rwcfg->mem_if_write_dqs_width,
3959 seq.rwcfg->mem_data_width, seq.rwcfg->mem_data_mask_width,
3960 seq.iocfg->delay_per_opa_tap,
3961 seq.iocfg->delay_per_dchain_tap);
3962 debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
3963 seq.iocfg->delay_per_dqs_en_dchain_tap,
3964 seq.iocfg->dll_chain_length);
3965 debug_cond(DLEVEL >= 1,
3966 "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3967 seq.iocfg->dqs_en_phase_max, seq.iocfg->dqdqs_out_phase_max,
3968 seq.iocfg->dqs_en_delay_max, seq.iocfg->dqs_in_delay_max);
3969 debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3970 seq.iocfg->io_in_delay_max, seq.iocfg->io_out1_delay_max,
3971 seq.iocfg->io_out2_delay_max);
3972 debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3973 seq.iocfg->dqs_in_reserve, seq.iocfg->dqs_out_reserve);
3974
3975 hc_initialize_rom_data();
3976
3977
3978 reg_file_set_stage(CAL_STAGE_NIL);
3979 reg_file_set_group(0);
3980
3981
3982
3983
3984
3985 seq.dyn_calib_steps = STATIC_CALIB_STEPS;
3986
3987
3988
3989
3990 if (!(seq.dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3991 seq.skip_delay_mask = 0xff;
3992 else
3993 seq.skip_delay_mask = 0x0;
3994
3995 pass = run_mem_calibrate(&seq);
3996 debug_mem_calibrate(&seq, pass);
3997 return pass;
3998}
3999