LXR uboot/drivers/ddr/fsl/mpc85xx_ddr

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright 2008 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <log.h>
   8#include <asm/io.h>
   9#include <fsl_ddr_sdram.h>
  10#include <linux/delay.h>
  11
  12#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  13#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  14#endif
  15
  16void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  17                             unsigned int ctrl_num, int step)
  18{
  19        unsigned int i;
  20        struct ccsr_ddr __iomem *ddr =
  21                (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
  22
  23        if (ctrl_num != 0) {
  24                printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  25                return;
  26        }
  27
  28        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  29                if (i == 0) {
  30                        out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  31                        out_be32(&ddr->cs0_config, regs->cs[i].config);
  32
  33                } else if (i == 1) {
  34                        out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  35                        out_be32(&ddr->cs1_config, regs->cs[i].config);
  36
  37                } else if (i == 2) {
  38                        out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  39                        out_be32(&ddr->cs2_config, regs->cs[i].config);
  40
  41                } else if (i == 3) {
  42                        out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  43                        out_be32(&ddr->cs3_config, regs->cs[i].config);
  44                }
  45        }
  46
  47        out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  48        out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  49        out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  50        out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  51#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541)
  52        out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  53#endif
  54
  55        /*
  56         * 200 painful micro-seconds must elapse between
  57         * the DDR clock setup and the DDR config enable.
  58         */
  59        udelay(200);
  60        asm volatile("sync;isync");
  61
  62        out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
  63
  64        asm("sync;isync;msync");
  65        udelay(500);
  66}
  67
  68#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  69/*
  70 * Initialize all of memory for ECC, then enable errors.
  71 */
  72
  73void
  74ddr_enable_ecc(unsigned int dram_size)
  75{
  76        struct ccsr_ddr __iomem *ddr =
  77                (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
  78
  79        dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
  80
  81        /*
  82         * Enable errors for ECC.
  83         */
  84        debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
  85        ddr->err_disable = 0x00000000;
  86        asm("sync;isync;msync");
  87        debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
  88}
  89
  90#endif  /* CONFIG_DDR_ECC  && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
  91