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2
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4
5
6#include "ddr3_init.h"
7#include "mv_ddr_common.h"
8#include "mv_ddr_training_db.h"
9#include "mv_ddr_regs.h"
10#include <log.h>
11#include <linux/delay.h>
12
13#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask])
14#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
15
16u32 window_mem_addr = 0;
17u32 phy_reg0_val = 0;
18u32 phy_reg1_val = 8;
19u32 phy_reg2_val = 0;
20u32 phy_reg3_val = PARAM_UNDEFINED;
21enum mv_ddr_freq low_freq = MV_DDR_FREQ_LOW_FREQ;
22enum mv_ddr_freq medium_freq;
23u32 debug_dunit = 0;
24u32 odt_additional = 1;
25u32 *dq_map_table = NULL;
26
27
28
29
30u32 odt_config = 1;
31
32u32 nominal_avs;
33u32 extension_avs;
34
35u32 is_pll_before_init = 0, is_adll_calib_before_init = 1, is_dfs_in_init = 0;
36u32 dfs_low_freq;
37
38u32 g_rtt_nom_cs0, g_rtt_nom_cs1;
39u8 calibration_update_control;
40
41enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
42enum auto_tune_stage training_stage = INIT_CONTROLLER;
43u32 finger_test = 0, p_finger_start = 11, p_finger_end = 64,
44 n_finger_start = 11, n_finger_end = 64,
45 p_finger_step = 3, n_finger_step = 3;
46u32 clamp_tbl[] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
47
48
49u32 mode_2t = 0xff;
50u32 xsb_validate_type = 0;
51u32 xsb_validation_base_address = 0xf000;
52u32 first_active_if = 0;
53u32 dfs_low_phy1 = 0x1f;
54u32 multicast_id = 0;
55int use_broadcast = 0;
56struct hws_tip_freq_config_info *freq_info_table = NULL;
57u8 is_cbe_required = 0;
58u32 debug_mode = 0;
59u32 delay_enable = 0;
60int rl_mid_freq_wa = 0;
61
62u32 effective_cs = 0;
63
64u32 vref_init_val = 0x4;
65u32 ck_delay = PARAM_UNDEFINED;
66
67
68u32 g_zpri_data = PARAM_UNDEFINED;
69u32 g_znri_data = PARAM_UNDEFINED;
70u32 g_zpri_ctrl = PARAM_UNDEFINED;
71u32 g_znri_ctrl = PARAM_UNDEFINED;
72
73u32 g_zpodt_data = PARAM_UNDEFINED;
74u32 g_znodt_data = PARAM_UNDEFINED;
75u32 g_zpodt_ctrl = PARAM_UNDEFINED;
76u32 g_znodt_ctrl = PARAM_UNDEFINED;
77
78u32 g_odt_config = PARAM_UNDEFINED;
79u32 g_rtt_nom = PARAM_UNDEFINED;
80u32 g_rtt_wr = PARAM_UNDEFINED;
81u32 g_dic = PARAM_UNDEFINED;
82u32 g_rtt_park = PARAM_UNDEFINED;
83
84u32 mask_tune_func = (SET_MEDIUM_FREQ_MASK_BIT |
85 WRITE_LEVELING_MASK_BIT |
86 LOAD_PATTERN_2_MASK_BIT |
87 READ_LEVELING_MASK_BIT |
88 SET_TARGET_FREQ_MASK_BIT |
89 WRITE_LEVELING_TF_MASK_BIT |
90 READ_LEVELING_TF_MASK_BIT |
91 CENTRALIZATION_RX_MASK_BIT |
92 CENTRALIZATION_TX_MASK_BIT);
93
94static int ddr3_tip_ddr3_training_main_flow(u32 dev_num);
95static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
96 u32 if_id, u32 cl_value, u32 cwl_value);
97static int ddr3_tip_ddr3_auto_tune(u32 dev_num);
98
99#ifdef ODT_TEST_SUPPORT
100static int odt_test(u32 dev_num, enum hws_algo_type algo_type);
101#endif
102
103int adll_calibration(u32 dev_num, enum hws_access_type access_type,
104 u32 if_id, enum mv_ddr_freq frequency);
105static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
106 u32 if_id, enum mv_ddr_freq frequency);
107
108static u8 mem_size_config[MV_DDR_DIE_CAP_LAST] = {
109 0x2,
110 0x3,
111 0x0,
112 0x4,
113 0x5,
114 0x0,
115 0x0,
116 0x0,
117 0x0
118};
119
120static u8 cs_mask2_num[] = { 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 };
121
122static struct reg_data odpg_default_value[] = {
123 {0x1034, 0x38000, MASK_ALL_BITS},
124 {0x1038, 0x0, MASK_ALL_BITS},
125 {0x10b0, 0x0, MASK_ALL_BITS},
126 {0x10b8, 0x0, MASK_ALL_BITS},
127 {0x10c0, 0x0, MASK_ALL_BITS},
128 {0x10f0, 0x0, MASK_ALL_BITS},
129 {0x10f4, 0x0, MASK_ALL_BITS},
130 {0x10f8, 0xff, MASK_ALL_BITS},
131 {0x10fc, 0xffff, MASK_ALL_BITS},
132 {0x1130, 0x0, MASK_ALL_BITS},
133 {0x1830, 0x2000000, MASK_ALL_BITS},
134 {0x14d0, 0x0, MASK_ALL_BITS},
135 {0x14d4, 0x0, MASK_ALL_BITS},
136 {0x14d8, 0x0, MASK_ALL_BITS},
137 {0x14dc, 0x0, MASK_ALL_BITS},
138 {0x1454, 0x0, MASK_ALL_BITS},
139 {0x1594, 0x0, MASK_ALL_BITS},
140 {0x1598, 0x0, MASK_ALL_BITS},
141 {0x159c, 0x0, MASK_ALL_BITS},
142 {0x15a0, 0x0, MASK_ALL_BITS},
143 {0x15a4, 0x0, MASK_ALL_BITS},
144 {0x15a8, 0x0, MASK_ALL_BITS},
145 {0x15ac, 0x0, MASK_ALL_BITS},
146 {0x1604, 0x0, MASK_ALL_BITS},
147 {0x1608, 0x0, MASK_ALL_BITS},
148 {0x160c, 0x0, MASK_ALL_BITS},
149 {0x1610, 0x0, MASK_ALL_BITS},
150 {0x1614, 0x0, MASK_ALL_BITS},
151 {0x1618, 0x0, MASK_ALL_BITS},
152 {0x1624, 0x0, MASK_ALL_BITS},
153 {0x1690, 0x0, MASK_ALL_BITS},
154 {0x1694, 0x0, MASK_ALL_BITS},
155 {0x1698, 0x0, MASK_ALL_BITS},
156 {0x169c, 0x0, MASK_ALL_BITS},
157 {0x14b8, 0x6f67, MASK_ALL_BITS},
158 {0x1630, 0x0, MASK_ALL_BITS},
159 {0x1634, 0x0, MASK_ALL_BITS},
160 {0x1638, 0x0, MASK_ALL_BITS},
161 {0x163c, 0x0, MASK_ALL_BITS},
162 {0x16b0, 0x0, MASK_ALL_BITS},
163 {0x16b4, 0x0, MASK_ALL_BITS},
164 {0x16b8, 0x0, MASK_ALL_BITS},
165 {0x16bc, 0x0, MASK_ALL_BITS},
166 {0x16c0, 0x0, MASK_ALL_BITS},
167 {0x16c4, 0x0, MASK_ALL_BITS},
168 {0x16c8, 0x0, MASK_ALL_BITS},
169 {0x16cc, 0x1, MASK_ALL_BITS},
170 {0x16f0, 0x1, MASK_ALL_BITS},
171 {0x16f4, 0x0, MASK_ALL_BITS},
172 {0x16f8, 0x0, MASK_ALL_BITS},
173 {0x16fc, 0x0, MASK_ALL_BITS}
174};
175
176
177struct mv_ddr_mr_data mr_data[] = {
178 {MRS0_CMD, MR0_REG},
179 {MRS1_CMD, MR1_REG},
180 {MRS2_CMD, MR2_REG},
181 {MRS3_CMD, MR3_REG}
182};
183
184
185static int ddr3_tip_pad_inv(void)
186{
187 u32 sphy, data;
188 u32 sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
189 u32 ck_swap_ctrl_sphy;
190 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
191
192 for (sphy = 0; sphy < sphy_max; sphy++) {
193 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy);
194 if (tm->interface_params[0].
195 as_bus_params[sphy].is_dqs_swap == 1) {
196 data = (INVERT_PAD << INV_PAD4_OFFS |
197 INVERT_PAD << INV_PAD5_OFFS);
198
199 ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST,
200 0, sphy,
201 DDR_PHY_DATA,
202 PHY_CTRL_PHY_REG,
203 data, data);
204 }
205
206 if (tm->interface_params[0].as_bus_params[sphy].
207 is_ck_swap == 1 && sphy == 0) {
208
209#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
210
211 data = (INVERT_PAD << INV_PAD2_OFFS |
212 INVERT_PAD << INV_PAD6_OFFS |
213 INVERT_PAD << INV_PAD4_OFFS |
214 INVERT_PAD << INV_PAD5_OFFS);
215 ck_swap_ctrl_sphy = CK_SWAP_CTRL_PHY_NUM;
216 ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST,
217 0, ck_swap_ctrl_sphy,
218 DDR_PHY_CONTROL,
219 PHY_CTRL_PHY_REG,
220 data, data);
221#else
222#pragma message "unknown platform to configure ddr clock swap"
223#endif
224 }
225 }
226
227 return MV_OK;
228}
229
230static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
231
232
233
234
235int ddr3_tip_tune_training_params(u32 dev_num,
236 struct tune_train_params *params)
237{
238 if (params->ck_delay != PARAM_UNDEFINED)
239 ck_delay = params->ck_delay;
240 if (params->phy_reg3_val != PARAM_UNDEFINED)
241 phy_reg3_val = params->phy_reg3_val;
242 if (params->g_rtt_nom != PARAM_UNDEFINED)
243 g_rtt_nom = params->g_rtt_nom;
244 if (params->g_rtt_wr != PARAM_UNDEFINED)
245 g_rtt_wr = params->g_rtt_wr;
246 if (params->g_dic != PARAM_UNDEFINED)
247 g_dic = params->g_dic;
248 if (params->g_odt_config != PARAM_UNDEFINED)
249 g_odt_config = params->g_odt_config;
250 if (params->g_zpri_data != PARAM_UNDEFINED)
251 g_zpri_data = params->g_zpri_data;
252 if (params->g_znri_data != PARAM_UNDEFINED)
253 g_znri_data = params->g_znri_data;
254 if (params->g_zpri_ctrl != PARAM_UNDEFINED)
255 g_zpri_ctrl = params->g_zpri_ctrl;
256 if (params->g_znri_ctrl != PARAM_UNDEFINED)
257 g_znri_ctrl = params->g_znri_ctrl;
258 if (params->g_zpodt_data != PARAM_UNDEFINED)
259 g_zpodt_data = params->g_zpodt_data;
260 if (params->g_znodt_data != PARAM_UNDEFINED)
261 g_znodt_data = params->g_znodt_data;
262 if (params->g_zpodt_ctrl != PARAM_UNDEFINED)
263 g_zpodt_ctrl = params->g_zpodt_ctrl;
264 if (params->g_znodt_ctrl != PARAM_UNDEFINED)
265 g_znodt_ctrl = params->g_znodt_ctrl;
266 if (params->g_rtt_park != PARAM_UNDEFINED)
267 g_rtt_park = params->g_rtt_park;
268
269
270 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
271 ("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
272 g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data,
273 g_zpodt_ctrl, g_znodt_ctrl, g_rtt_nom, g_dic, g_odt_config, g_rtt_wr));
274
275 return MV_OK;
276}
277
278
279
280
281int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
282{
283 u32 data, addr_hi, data_high;
284 u32 mem_index;
285 u32 clk_enable;
286 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
287
288 if (tm->clk_enable & (1 << cs_num))
289 clk_enable = 1;
290 else
291 clk_enable = enable;
292
293 if (enable == 1) {
294 data = (tm->interface_params[if_id].bus_width ==
295 MV_DDR_DEV_WIDTH_8BIT) ? 0 : 1;
296 CHECK_STATUS(ddr3_tip_if_write
297 (dev_num, ACCESS_TYPE_UNICAST, if_id,
298 SDRAM_ADDR_CTRL_REG, (data << (cs_num * 4)),
299 0x3 << (cs_num * 4)));
300 mem_index = tm->interface_params[if_id].memory_size;
301
302 addr_hi = mem_size_config[mem_index] & 0x3;
303 CHECK_STATUS(ddr3_tip_if_write
304 (dev_num, ACCESS_TYPE_UNICAST, if_id,
305 SDRAM_ADDR_CTRL_REG,
306 (addr_hi << (2 + cs_num * 4)),
307 0x3 << (2 + cs_num * 4)));
308
309 data_high = (mem_size_config[mem_index] & 0x4) >> 2;
310 CHECK_STATUS(ddr3_tip_if_write
311 (dev_num, ACCESS_TYPE_UNICAST, if_id,
312 SDRAM_ADDR_CTRL_REG,
313 data_high << (20 + cs_num), 1 << (20 + cs_num)));
314
315
316 CHECK_STATUS(ddr3_tip_if_write
317 (dev_num, ACCESS_TYPE_UNICAST, if_id,
318 SDRAM_ADDR_CTRL_REG, 1 << (16 + cs_num),
319 1 << (16 + cs_num)));
320 }
321 switch (cs_num) {
322 case 0:
323 case 1:
324 case 2:
325 CHECK_STATUS(ddr3_tip_if_write
326 (dev_num, ACCESS_TYPE_UNICAST, if_id,
327 DUNIT_CTRL_LOW_REG, (clk_enable << (cs_num + 11)),
328 1 << (cs_num + 11)));
329 break;
330 case 3:
331 CHECK_STATUS(ddr3_tip_if_write
332 (dev_num, ACCESS_TYPE_UNICAST, if_id,
333 DUNIT_CTRL_LOW_REG, (clk_enable << 15), 1 << 15));
334 break;
335 }
336
337 return MV_OK;
338}
339
340
341
342
343int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm)
344{
345 u32 if_id;
346 u32 cs_num;
347 u32 t_ckclk = 0, t_wr = 0, t2t = 0;
348 u32 data_value = 0, cs_cnt = 0,
349 mem_mask = 0, bus_index = 0;
350 enum mv_ddr_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N;
351 u32 cs_mask = 0;
352 u32 cl_value = 0, cwl_val = 0;
353 u32 bus_cnt = 0, adll_tap = 0;
354 enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
355 u32 data_read[MAX_INTERFACE_NUM];
356 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
357 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
358 enum mv_ddr_timing timing;
359 enum mv_ddr_freq freq = tm->interface_params[0].memory_freq;
360
361 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
362 ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
363 init_cntr_prm->do_mrs_phy,
364 init_cntr_prm->is_ctrl64_bit));
365
366 if (init_cntr_prm->init_phy == 1) {
367 CHECK_STATUS(ddr3_tip_configure_phy(dev_num));
368 }
369
370 if (generic_init_controller == 1) {
371 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
372 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
373 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
374 ("active IF %d\n", if_id));
375 mem_mask = 0;
376 for (bus_index = 0;
377 bus_index < octets_per_if_num;
378 bus_index++) {
379 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index);
380 mem_mask |=
381 tm->interface_params[if_id].
382 as_bus_params[bus_index].mirror_enable_bitmask;
383 }
384
385 if (mem_mask != 0) {
386 CHECK_STATUS(ddr3_tip_if_write
387 (dev_num, ACCESS_TYPE_MULTICAST,
388 if_id, DUAL_DUNIT_CFG_REG, 0,
389 0x8));
390 }
391
392 speed_bin_index =
393 tm->interface_params[if_id].
394 speed_bin_index;
395
396
397 t_ckclk = (MEGA / mv_ddr_freq_get(freq));
398
399 if (MV_DDR_IS_HALF_BUS_DRAM_MODE(tm->bus_act_mask, octets_per_if_num))
400 data_value = (0x4000 | 0 | 0x1000000) & ~(1 << 26);
401 else
402 data_value = (0x4000 | 0x8000 | 0x1000000) & ~(1 << 26);
403
404
405
406 CHECK_STATUS(ddr3_tip_if_write
407 (dev_num, access_type, if_id,
408 SDRAM_CFG_REG, data_value,
409 0x100c000));
410
411
412 CHECK_STATUS(ddr3_tip_if_write
413 (dev_num, access_type, if_id,
414 SDRAM_OPEN_PAGES_CTRL_REG, (1 << 10),
415 (1 << 10)));
416
417
418 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
419 SDRAM_CFG_REG,
420 0x0 << PUP_RST_DIVIDER_OFFS,
421 PUP_RST_DIVIDER_MASK << PUP_RST_DIVIDER_OFFS));
422
423 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
424 SDRAM_CFG_REG,
425 0x1 << PUP_RST_DIVIDER_OFFS,
426 PUP_RST_DIVIDER_MASK << PUP_RST_DIVIDER_OFFS));
427
428
429
430
431
432
433 CHECK_STATUS(ddr3_tip_if_write
434 (dev_num, access_type, if_id,
435 DRAM_PHY_CFG_REG, 0x28, 0x3e));
436 if (init_cntr_prm->is_ctrl64_bit) {
437
438 CHECK_STATUS(ddr3_tip_if_write
439 (dev_num, access_type, if_id,
440 DRAM_PHY_CFG_REG, 0x0,
441 0xff80));
442 }
443
444
445
446 CHECK_STATUS(ddr3_tip_if_write
447 (dev_num, access_type, if_id,
448 MAIN_PADS_CAL_MACH_CTRL_REG, 0x1200c,
449 0x7dffe01c));
450 CHECK_STATUS(ddr3_tip_if_write
451 (dev_num, access_type, if_id,
452 MAIN_PADS_CAL_MACH_CTRL_REG,
453 calibration_update_control << 3, 0x3 << 3));
454
455
456 CHECK_STATUS(ddr3_tip_if_write
457 (dev_num, access_type, if_id,
458 MAIN_PADS_CAL_MACH_CTRL_REG, 0x1, 0x1));
459 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) {
460
461
462 CHECK_STATUS(ddr3_tip_if_write
463 (dev_num, access_type, if_id,
464 DDR3_RANK_CTRL_REG, 0x27, MASK_ALL_BITS));
465 }
466
467 cs_mask = 0;
468 data_value = 0x7;
469
470
471
472
473
474
475
476
477
478
479
480 data_value =
481 (tm->interface_params[if_id].
482 bus_width == MV_DDR_DEV_WIDTH_8BIT) ? 0 : 1;
483
484
485 for (bus_cnt = 0;
486 bus_cnt < octets_per_if_num;
487 bus_cnt++) {
488 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
489 cs_mask |=
490 tm->interface_params[if_id].
491 as_bus_params[bus_cnt].cs_bitmask;
492 }
493 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
494 ("Init_controller IF %d cs_mask %d\n",
495 if_id, cs_mask));
496
497
498
499
500
501
502 for (cs_cnt = 0; cs_cnt < MAX_CS_NUM; cs_cnt++) {
503 ddr3_tip_configure_cs(dev_num, if_id, cs_cnt,
504 ((cs_mask & (1 << cs_cnt)) ? 1
505 : 0));
506 }
507
508 if (init_cntr_prm->do_mrs_phy) {
509
510
511
512
513
514
515
516
517
518 cl_value =
519 tm->interface_params[if_id].
520 cas_l;
521 cwl_val =
522 tm->interface_params[if_id].
523 cas_wl;
524 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
525 ("cl_value 0x%x cwl_val 0x%x\n",
526 cl_value, cwl_val));
527
528 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get
529 (speed_bin_index,
530 SPEED_BIN_TWR), t_ckclk);
531
532 data_value =
533 ((cl_mask_table[cl_value] & 0x1) << 2) |
534 ((cl_mask_table[cl_value] & 0xe) << 3);
535 CHECK_STATUS(ddr3_tip_if_write
536 (dev_num, access_type, if_id,
537 MR0_REG, data_value,
538 (0x7 << 4) | (1 << 2)));
539 CHECK_STATUS(ddr3_tip_if_write
540 (dev_num, access_type, if_id,
541 MR0_REG, twr_mask_table[t_wr] << 9,
542 0x7 << 9));
543
544
545
546
547
548 CHECK_STATUS(ddr3_tip_if_write
549 (dev_num, ACCESS_TYPE_MULTICAST,
550 PARAM_NOT_CARE, MR1_REG,
551 g_dic | g_rtt_nom, 0x266));
552
553
554
555
556
557
558
559 data_value = (cwl_mask_table[cwl_val] << 3);
560 data_value |=
561 ((tm->interface_params[if_id].
562 interface_temp ==
563 MV_DDR_TEMP_HIGH) ? (1 << 7) : 0);
564 data_value |= g_rtt_wr;
565 CHECK_STATUS(ddr3_tip_if_write
566 (dev_num, access_type, if_id,
567 MR2_REG, data_value,
568 (0x7 << 3) | (0x1 << 7) | (0x3 <<
569 9)));
570 }
571
572 ddr3_tip_write_odt(dev_num, access_type, if_id,
573 cl_value, cwl_val);
574 ddr3_tip_set_timing(dev_num, access_type, if_id, freq);
575
576 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) {
577 CHECK_STATUS(ddr3_tip_if_write
578 (dev_num, access_type, if_id,
579 DUNIT_CTRL_HIGH_REG, 0x1000119,
580 0x100017F));
581 } else {
582 CHECK_STATUS(ddr3_tip_if_write
583 (dev_num, access_type, if_id,
584 DUNIT_CTRL_HIGH_REG, 0x600177 |
585 (init_cntr_prm->is_ctrl64_bit ?
586 CPU_INTERJECTION_ENA_SPLIT_ENA << CPU_INTERJECTION_ENA_OFFS :
587 CPU_INTERJECTION_ENA_SPLIT_DIS << CPU_INTERJECTION_ENA_OFFS),
588 0x1600177 | CPU_INTERJECTION_ENA_MASK <<
589 CPU_INTERJECTION_ENA_OFFS));
590 }
591
592
593 CHECK_STATUS(ddr3_tip_if_write
594 (dev_num, access_type, if_id,
595 DUNIT_CTRL_HIGH_REG,
596 (init_cntr_prm->msys_init << 7), (1 << 7)));
597
598 timing = tm->interface_params[if_id].timing;
599
600 if (mode_2t != 0xff) {
601 t2t = mode_2t;
602 } else if (timing != MV_DDR_TIM_DEFAULT) {
603 t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
604 } else {
605
606 cs_num = mv_ddr_cs_num_get();
607 t2t = (cs_num == 1) ? 0 : 1;
608 }
609
610 CHECK_STATUS(ddr3_tip_if_write
611 (dev_num, access_type, if_id,
612 DUNIT_CTRL_LOW_REG, t2t << 3,
613 0x3 << 3));
614 CHECK_STATUS(ddr3_tip_if_write
615 (dev_num, access_type, if_id,
616 DDR_TIMING_REG, 0x28 << 9, 0x3f << 9));
617 CHECK_STATUS(ddr3_tip_if_write
618 (dev_num, access_type, if_id,
619 DDR_TIMING_REG, 0xa << 21, 0xff << 21));
620
621
622
623 CHECK_STATUS(ddr3_tip_if_write
624 (dev_num, access_type, if_id,
625 ZQC_CFG_REG, (AUTO_ZQC_TIMING | (2 << 20)),
626 0x3fffff));
627 CHECK_STATUS(ddr3_tip_if_read
628 (dev_num, access_type, if_id,
629 DRAM_PHY_CFG_REG, data_read, 0x30));
630 data_value =
631 (data_read[if_id] == 0) ? (1 << 11) : 0;
632 CHECK_STATUS(ddr3_tip_if_write
633 (dev_num, access_type, if_id,
634 DUNIT_CTRL_HIGH_REG, data_value,
635 (1 << 11)));
636
637
638 CHECK_STATUS(ddr3_tip_if_write
639 (dev_num, ACCESS_TYPE_MULTICAST,
640 PARAM_NOT_CARE, 0x1494, g_odt_config,
641 MASK_ALL_BITS));
642
643 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_3) {
644 CHECK_STATUS(ddr3_tip_if_write
645 (dev_num, access_type, if_id,
646 0x14a8, 0x900, 0x900));
647
648 CHECK_STATUS(ddr3_tip_if_write
649 (dev_num, access_type, if_id,
650 0x16d0, 0, 0x8000));
651 }
652 }
653 }
654
655 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
656 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
657 CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id));
658
659 if (init_cntr_prm->do_mrs_phy)
660 ddr3_tip_pad_inv();
661
662
663 CHECK_STATUS(ddr3_tip_if_write
664 (dev_num, access_type, if_id,
665 MAIN_PADS_CAL_MACH_CTRL_REG, 0x0, 0x1));
666 CHECK_STATUS(ddr3_tip_if_write
667 (dev_num, access_type, if_id,
668 MAIN_PADS_CAL_MACH_CTRL_REG,
669 calibration_update_control << 3, 0x3 << 3));
670 }
671
672
673 if (delay_enable != 0) {
674 adll_tap = MEGA / (mv_ddr_freq_get(freq) * 64);
675 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
676 }
677
678 return MV_OK;
679}
680
681
682
683
684static int ddr3_tip_rev2_rank_control(u32 dev_num, u32 if_id)
685{
686 u32 data_value = 0, bus_cnt = 0;
687 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
688 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
689
690 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) {
691 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
692 data_value |= tm->interface_params[if_id].as_bus_params[bus_cnt].
693 cs_bitmask;
694
695 if (tm->interface_params[if_id].as_bus_params[bus_cnt].
696 mirror_enable_bitmask == 1) {
697
698
699
700
701 if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
702 cs_bitmask & 0x1) != 0) {
703 data_value |= tm->interface_params[if_id].
704 as_bus_params[bus_cnt].
705 mirror_enable_bitmask << 4;
706 }
707
708 if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
709 cs_bitmask & 0x2) != 0) {
710 data_value |= tm->interface_params[if_id].
711 as_bus_params[bus_cnt].
712 mirror_enable_bitmask << 5;
713 }
714
715 if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
716 cs_bitmask & 0x4) != 0) {
717 data_value |= tm->interface_params[if_id].
718 as_bus_params[bus_cnt].
719 mirror_enable_bitmask << 6;
720 }
721
722 if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
723 cs_bitmask & 0x8) != 0) {
724 data_value |= tm->interface_params[if_id].
725 as_bus_params[bus_cnt].
726 mirror_enable_bitmask << 7;
727 }
728 }
729 }
730
731 CHECK_STATUS(ddr3_tip_if_write
732 (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG,
733 data_value, 0xff));
734
735 return MV_OK;
736}
737
738static int ddr3_tip_rev3_rank_control(u32 dev_num, u32 if_id)
739{
740 u32 data_value = 0, bus_cnt;
741 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
742 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
743
744 for (bus_cnt = 1; bus_cnt < octets_per_if_num; bus_cnt++) {
745 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
746 if ((tm->interface_params[if_id].
747 as_bus_params[0].cs_bitmask !=
748 tm->interface_params[if_id].
749 as_bus_params[bus_cnt].cs_bitmask) ||
750 (tm->interface_params[if_id].
751 as_bus_params[0].mirror_enable_bitmask !=
752 tm->interface_params[if_id].
753 as_bus_params[bus_cnt].mirror_enable_bitmask))
754 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
755 ("WARNING:Wrong configuration for pup #%d CS mask and CS mirroring for all pups should be the same\n",
756 bus_cnt));
757 }
758
759 data_value |= tm->interface_params[if_id].
760 as_bus_params[0].cs_bitmask;
761 data_value |= tm->interface_params[if_id].
762 as_bus_params[0].mirror_enable_bitmask << 4;
763
764 CHECK_STATUS(ddr3_tip_if_write
765 (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG,
766 data_value, 0xff));
767
768 return MV_OK;
769}
770
771static int ddr3_tip_rank_control(u32 dev_num, u32 if_id)
772{
773 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_2)
774 return ddr3_tip_rev2_rank_control(dev_num, if_id);
775 else
776 return ddr3_tip_rev3_rank_control(dev_num, if_id);
777}
778
779
780
781
782int ddr3_tip_validate_algo_var(u32 value, u32 fail_value, char *var_name)
783{
784 if (value == fail_value) {
785 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
786 ("Error: %s is not initialized (Algo Components Validation)\n",
787 var_name));
788 return 0;
789 }
790
791 return 1;
792}
793
794int ddr3_tip_validate_algo_ptr(void *ptr, void *fail_value, char *ptr_name)
795{
796 if (ptr == fail_value) {
797 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
798 ("Error: %s is not initialized (Algo Components Validation)\n",
799 ptr_name));
800 return 0;
801 }
802
803 return 1;
804}
805
806int ddr3_tip_validate_algo_components(u8 dev_num)
807{
808 int status = 1;
809
810
811 status &= ddr3_tip_validate_algo_var(ck_delay, PARAM_UNDEFINED, "ck_delay");
812 status &= ddr3_tip_validate_algo_var(phy_reg3_val, PARAM_UNDEFINED, "phy_reg3_val");
813 status &= ddr3_tip_validate_algo_var(g_rtt_nom, PARAM_UNDEFINED, "g_rtt_nom");
814 status &= ddr3_tip_validate_algo_var(g_dic, PARAM_UNDEFINED, "g_dic");
815 status &= ddr3_tip_validate_algo_var(odt_config, PARAM_UNDEFINED, "odt_config");
816 status &= ddr3_tip_validate_algo_var(g_zpri_data, PARAM_UNDEFINED, "g_zpri_data");
817 status &= ddr3_tip_validate_algo_var(g_znri_data, PARAM_UNDEFINED, "g_znri_data");
818 status &= ddr3_tip_validate_algo_var(g_zpri_ctrl, PARAM_UNDEFINED, "g_zpri_ctrl");
819 status &= ddr3_tip_validate_algo_var(g_znri_ctrl, PARAM_UNDEFINED, "g_znri_ctrl");
820 status &= ddr3_tip_validate_algo_var(g_zpodt_data, PARAM_UNDEFINED, "g_zpodt_data");
821 status &= ddr3_tip_validate_algo_var(g_znodt_data, PARAM_UNDEFINED, "g_znodt_data");
822 status &= ddr3_tip_validate_algo_var(g_zpodt_ctrl, PARAM_UNDEFINED, "g_zpodt_ctrl");
823 status &= ddr3_tip_validate_algo_var(g_znodt_ctrl, PARAM_UNDEFINED, "g_znodt_ctrl");
824
825
826 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_dunit_mux_select_func,
827 NULL, "tip_dunit_mux_select_func");
828 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_write,
829 NULL, "mv_ddr_dunit_write");
830 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_read,
831 NULL, "mv_ddr_dunit_read");
832 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_write,
833 NULL, "mv_ddr_phy_write");
834 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_read,
835 NULL, "mv_ddr_phy_read");
836 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_freq_config_info_func,
837 NULL, "tip_get_freq_config_info_func");
838 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_set_freq_divider_func,
839 NULL, "tip_set_freq_divider_func");
840 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_clock_ratio,
841 NULL, "tip_get_clock_ratio");
842
843 status &= ddr3_tip_validate_algo_ptr(dq_map_table, NULL, "dq_map_table");
844 status &= ddr3_tip_validate_algo_var(dfs_low_freq, 0, "dfs_low_freq");
845
846 return (status == 1) ? MV_OK : MV_NOT_INITIALIZED;
847}
848
849
850int ddr3_pre_algo_config(void)
851{
852 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
853
854
855 if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) {
856
857 CHECK_STATUS(ddr3_tip_if_write
858 (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
859 DRAM_PINS_MUX_REG, 0x100, 0x100));
860 }
861
862
863 if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
864 (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) ||
865 (DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))) {
866
867 CHECK_STATUS(ddr3_tip_if_write
868 (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
869 TRAINING_SW_2_REG, 0x100, 0x100));
870
871 CHECK_STATUS(ddr3_tip_if_write
872 (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
873 SDRAM_CFG_REG, 0x40000, 0x40000));
874
875 CHECK_STATUS(ddr3_tip_if_write
876 (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
877 TRAINING_SW_2_REG, 0x0, 0x2));
878 }
879
880 return MV_OK;
881}
882
883int ddr3_post_algo_config(void)
884{
885 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
886 int status;
887
888 status = ddr3_post_run_alg();
889 if (MV_OK != status) {
890 printf("DDR3 Post Run Alg - FAILED 0x%x\n", status);
891 return status;
892 }
893
894
895 if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
896 (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) ||
897 (DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))) {
898
899 CHECK_STATUS(ddr3_tip_if_write
900 (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
901 TRAINING_SW_2_REG, 0x0, 0x100));
902
903 }
904
905 return MV_OK;
906}
907
908
909
910
911int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type)
912{
913 int status = MV_OK;
914
915 status = ddr3_pre_algo_config();
916 if (MV_OK != status) {
917 printf("DDR3 Pre Algo Config - FAILED 0x%x\n", status);
918 return status;
919 }
920
921#ifdef ODT_TEST_SUPPORT
922 if (finger_test == 1)
923 return odt_test(dev_num, algo_type);
924#endif
925
926 if (algo_type == ALGO_TYPE_DYNAMIC) {
927 status = ddr3_tip_ddr3_auto_tune(dev_num);
928 }
929
930 if (status != MV_OK) {
931 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
932 ("******** DRAM initialization Failed (res 0x%x) ********\n",
933 status));
934 return status;
935 }
936
937 status = ddr3_post_algo_config();
938 if (MV_OK != status) {
939 printf("DDR3 Post Algo Config - FAILED 0x%x\n", status);
940 return status;
941 }
942
943 return status;
944}
945
946#ifdef ODT_TEST_SUPPORT
947
948
949
950static int odt_test(u32 dev_num, enum hws_algo_type algo_type)
951{
952 int ret = MV_OK, ret_tune = MV_OK;
953 int pfinger_val = 0, nfinger_val;
954
955 for (pfinger_val = p_finger_start; pfinger_val <= p_finger_end;
956 pfinger_val += p_finger_step) {
957 for (nfinger_val = n_finger_start; nfinger_val <= n_finger_end;
958 nfinger_val += n_finger_step) {
959 if (finger_test != 0) {
960 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
961 ("pfinger_val %d nfinger_val %d\n",
962 pfinger_val, nfinger_val));
963
964
965
966
967 g_zpodt_data = pfinger_val;
968 g_znodt_data = nfinger_val;
969 }
970
971 if (algo_type == ALGO_TYPE_DYNAMIC) {
972 ret = ddr3_tip_ddr3_auto_tune(dev_num);
973 }
974 }
975 }
976
977 if (ret_tune != MV_OK) {
978 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
979 ("Run_alg: tuning failed %d\n", ret_tune));
980 ret = (ret == MV_OK) ? ret_tune : ret;
981 }
982
983 return ret;
984}
985#endif
986
987
988
989
990int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable)
991{
992 return config_func_info[dev_num].
993 tip_dunit_mux_select_func((u8)dev_num, enable);
994}
995
996
997
998
999int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
1000 u32 if_id, u32 reg_addr, u32 data_value, u32 mask)
1001{
1002 config_func_info[dev_num].mv_ddr_dunit_write(reg_addr, mask, data_value);
1003
1004 return MV_OK;
1005}
1006
1007
1008
1009
1010int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
1011 u32 if_id, u32 reg_addr, u32 *data, u32 mask)
1012{
1013 config_func_info[dev_num].mv_ddr_dunit_read(reg_addr, mask, data);
1014
1015 return MV_OK;
1016}
1017
1018
1019
1020
1021int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
1022 u32 if_id, u32 exp_value, u32 mask, u32 offset,
1023 u32 poll_tries)
1024{
1025 u32 poll_cnt = 0, interface_num = 0, start_if, end_if;
1026 u32 read_data[MAX_INTERFACE_NUM];
1027 int ret;
1028 int is_fail = 0, is_if_fail;
1029 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1030
1031 if (access_type == ACCESS_TYPE_MULTICAST) {
1032 start_if = 0;
1033 end_if = MAX_INTERFACE_NUM - 1;
1034 } else {
1035 start_if = if_id;
1036 end_if = if_id;
1037 }
1038
1039 for (interface_num = start_if; interface_num <= end_if; interface_num++) {
1040
1041 VALIDATE_IF_ACTIVE(tm->if_act_mask, interface_num);
1042
1043 is_if_fail = 0;
1044 for (poll_cnt = 0; poll_cnt < poll_tries; poll_cnt++) {
1045 ret =
1046 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST,
1047 interface_num, offset, read_data,
1048 mask);
1049 if (ret != MV_OK)
1050 return ret;
1051
1052 if (read_data[interface_num] == exp_value)
1053 break;
1054 }
1055
1056 if (poll_cnt >= poll_tries) {
1057 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1058 ("max poll IF #%d\n", interface_num));
1059 is_fail = 1;
1060 is_if_fail = 1;
1061 }
1062
1063 training_result[training_stage][interface_num] =
1064 (is_if_fail == 1) ? TEST_FAILED : TEST_SUCCESS;
1065 }
1066
1067 return (is_fail == 0) ? MV_OK : MV_FAIL;
1068}
1069
1070
1071
1072
1073int ddr3_tip_bus_read(u32 dev_num, u32 if_id,
1074 enum hws_access_type phy_access, u32 phy_id,
1075 enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data)
1076{
1077 return config_func_info[dev_num].
1078 mv_ddr_phy_read(phy_access, phy_id, phy_type, reg_addr, data);
1079}
1080
1081
1082
1083
1084int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,
1085 u32 if_id, enum hws_access_type phy_access,
1086 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
1087 u32 data_value)
1088{
1089 return config_func_info[dev_num].
1090 mv_ddr_phy_write(phy_access, phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE);
1091}
1092
1093
1094
1095
1096
1097int ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type,
1098 u32 interface_id, u32 phy_id,
1099 enum hws_ddr_phy phy_type, u32 reg_addr,
1100 u32 data_value, u32 reg_mask)
1101{
1102 u32 data_val = 0, if_id, start_if, end_if;
1103 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1104
1105 if (access_type == ACCESS_TYPE_MULTICAST) {
1106 start_if = 0;
1107 end_if = MAX_INTERFACE_NUM - 1;
1108 } else {
1109 start_if = interface_id;
1110 end_if = interface_id;
1111 }
1112
1113 for (if_id = start_if; if_id <= end_if; if_id++) {
1114 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1115 CHECK_STATUS(ddr3_tip_bus_read
1116 (dev_num, if_id, ACCESS_TYPE_UNICAST, phy_id,
1117 phy_type, reg_addr, &data_val));
1118 data_value = (data_val & (~reg_mask)) | (data_value & reg_mask);
1119 CHECK_STATUS(ddr3_tip_bus_write
1120 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1121 ACCESS_TYPE_UNICAST, phy_id, phy_type, reg_addr,
1122 data_value));
1123 }
1124
1125 return MV_OK;
1126}
1127
1128
1129
1130
1131int adll_calibration(u32 dev_num, enum hws_access_type access_type,
1132 u32 if_id, enum mv_ddr_freq frequency)
1133{
1134 struct hws_tip_freq_config_info freq_config_info;
1135 u32 bus_cnt = 0;
1136 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1137 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1138
1139
1140 CHECK_STATUS(ddr3_tip_if_write
1141 (dev_num, access_type, if_id, SDRAM_CFG_REG,
1142 0, 0x10000000));
1143 mdelay(10);
1144 CHECK_STATUS(ddr3_tip_if_write
1145 (dev_num, access_type, if_id, SDRAM_CFG_REG,
1146 0x10000000, 0x10000000));
1147
1148 CHECK_STATUS(config_func_info[dev_num].
1149 tip_get_freq_config_info_func((u8)dev_num, frequency,
1150 &freq_config_info));
1151
1152 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) {
1153 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
1154 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1155 (dev_num, access_type, if_id, bus_cnt,
1156 DDR_PHY_DATA, ADLL_CFG0_PHY_REG,
1157 freq_config_info.bw_per_freq << 8, 0x700));
1158 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1159 (dev_num, access_type, if_id, bus_cnt,
1160 DDR_PHY_DATA, ADLL_CFG2_PHY_REG,
1161 freq_config_info.rate_per_freq, 0x7));
1162 }
1163
1164 for (bus_cnt = 0; bus_cnt < DDR_IF_CTRL_SUBPHYS_NUM; bus_cnt++) {
1165 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1166 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt,
1167 DDR_PHY_CONTROL, ADLL_CFG0_PHY_REG,
1168 freq_config_info.bw_per_freq << 8, 0x700));
1169 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1170 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt,
1171 DDR_PHY_CONTROL, ADLL_CFG2_PHY_REG,
1172 freq_config_info.rate_per_freq, 0x7));
1173 }
1174
1175
1176 CHECK_STATUS(ddr3_tip_if_write
1177 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG,
1178 0, (0x80000000 | 0x40000000)));
1179 mdelay(100 / (mv_ddr_freq_get(frequency)) / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ));
1180 CHECK_STATUS(ddr3_tip_if_write
1181 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG,
1182 (0x80000000 | 0x40000000), (0x80000000 | 0x40000000)));
1183
1184
1185 if (ddr3_tip_if_polling(dev_num, access_type, if_id,
1186 0x3ff03ff, 0x3ff03ff, PHY_LOCK_STATUS_REG,
1187 MAX_POLLING_ITERATIONS) != MV_OK) {
1188 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1189 ("Freq_set: DDR3 poll failed(1)"));
1190 }
1191
1192
1193 CHECK_STATUS(ddr3_tip_if_write
1194 (dev_num, access_type, if_id, SDRAM_CFG_REG,
1195 0, 0x60000000));
1196 mdelay(10);
1197 CHECK_STATUS(ddr3_tip_if_write
1198 (dev_num, access_type, if_id, SDRAM_CFG_REG,
1199 0x60000000, 0x60000000));
1200
1201 return MV_OK;
1202}
1203
1204int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
1205 u32 if_id, enum mv_ddr_freq frequency)
1206{
1207 u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0,
1208 bus_cnt = 0, t_wr = 0, t_ckclk = 0,
1209 cnt_id;
1210 u32 end_if, start_if;
1211 u32 bus_index = 0;
1212 int is_dll_off = 0;
1213 enum mv_ddr_speed_bin speed_bin_index = 0;
1214 struct hws_tip_freq_config_info freq_config_info;
1215 enum hws_result *flow_result = training_result[training_stage];
1216 u32 adll_tap = 0;
1217 u32 cs_num;
1218 u32 t2t;
1219 u32 cs_mask[MAX_INTERFACE_NUM];
1220 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1221 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1222 unsigned int tclk;
1223 enum mv_ddr_timing timing = tm->interface_params[if_id].timing;
1224 u32 freq = mv_ddr_freq_get(frequency);
1225
1226 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
1227 ("dev %d access %d IF %d freq %d\n", dev_num,
1228 access_type, if_id, frequency));
1229
1230 if (frequency == MV_DDR_FREQ_LOW_FREQ)
1231 is_dll_off = 1;
1232 if (access_type == ACCESS_TYPE_MULTICAST) {
1233 start_if = 0;
1234 end_if = MAX_INTERFACE_NUM - 1;
1235 } else {
1236 start_if = if_id;
1237 end_if = if_id;
1238 }
1239
1240
1241
1242 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1243
1244 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1245 cs_mask[if_id] = CS_BIT_MASK;
1246 training_result[training_stage][if_id] = TEST_SUCCESS;
1247 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs,
1248 &cs_mask[if_id]);
1249 }
1250
1251
1252
1253
1254
1255
1256 for (if_id = start_if; if_id <= end_if; if_id++) {
1257 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1258
1259 flow_result[if_id] = TEST_SUCCESS;
1260 speed_bin_index =
1261 tm->interface_params[if_id].speed_bin_index;
1262 if (tm->interface_params[if_id].memory_freq ==
1263 frequency) {
1264 cl_value =
1265 tm->interface_params[if_id].cas_l;
1266 cwl_value =
1267 tm->interface_params[if_id].cas_wl;
1268 } else if (tm->cfg_src == MV_DDR_CFG_SPD) {
1269 tclk = 1000000 / freq;
1270 cl_value = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);
1271 if (cl_value == 0) {
1272 printf("mv_ddr: unsupported cas latency value found\n");
1273 return MV_FAIL;
1274 }
1275 cwl_value = mv_ddr_cwl_calc(tclk);
1276 if (cwl_value == 0) {
1277 printf("mv_ddr: unsupported cas write latency value found\n");
1278 return MV_FAIL;
1279 }
1280 } else {
1281 cl_value = mv_ddr_cl_val_get(speed_bin_index, frequency);
1282 cwl_value = mv_ddr_cwl_val_get(speed_bin_index, frequency);
1283 }
1284
1285 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
1286 ("Freq_set dev 0x%x access 0x%x if 0x%x freq 0x%x speed %d:\n\t",
1287 dev_num, access_type, if_id,
1288 frequency, speed_bin_index));
1289
1290 for (cnt_id = 0; cnt_id < MV_DDR_FREQ_LAST; cnt_id++) {
1291 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
1292 ("%d ", mv_ddr_cl_val_get(speed_bin_index, cnt_id)));
1293 }
1294
1295 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("\n"));
1296 mem_mask = 0;
1297 for (bus_index = 0; bus_index < octets_per_if_num;
1298 bus_index++) {
1299 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index);
1300 mem_mask |=
1301 tm->interface_params[if_id].
1302 as_bus_params[bus_index].mirror_enable_bitmask;
1303 }
1304
1305 if (mem_mask != 0) {
1306
1307 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1308 if_id,
1309 DUAL_DUNIT_CFG_REG, 0, 0x8));
1310 }
1311
1312
1313 if (is_dll_off == 1) {
1314 CHECK_STATUS(ddr3_tip_if_write
1315 (dev_num, access_type, if_id,
1316 DFS_REG, 0x1, 0x1));
1317 } else {
1318 CHECK_STATUS(ddr3_tip_if_write
1319 (dev_num, access_type, if_id,
1320 DFS_REG, 0, 0x1));
1321 }
1322
1323 CHECK_STATUS(ddr3_tip_if_write
1324 (dev_num, access_type, if_id,
1325 DUNIT_MMASK_REG, 0, 0x1));
1326
1327 CHECK_STATUS(ddr3_tip_if_write
1328 (dev_num, access_type, if_id,
1329 DFS_REG, 0x2, 0x2));
1330
1331
1332 if (is_dll_off == 1) {
1333 CHECK_STATUS(ddr3_tip_if_write
1334 (dev_num, access_type, if_id,
1335 0x1874, 0, 0x244));
1336 CHECK_STATUS(ddr3_tip_if_write
1337 (dev_num, access_type, if_id,
1338 0x1884, 0, 0x244));
1339 CHECK_STATUS(ddr3_tip_if_write
1340 (dev_num, access_type, if_id,
1341 0x1894, 0, 0x244));
1342 CHECK_STATUS(ddr3_tip_if_write
1343 (dev_num, access_type, if_id,
1344 0x18a4, 0, 0x244));
1345 }
1346
1347
1348 CHECK_STATUS(ddr3_tip_if_write
1349 (dev_num, access_type, if_id, DFS_REG, 0x4,
1350 0x4));
1351
1352 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST,
1353 if_id, 0x8, 0x8, DFS_REG,
1354 MAX_POLLING_ITERATIONS) != MV_OK) {
1355 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1356 ("Freq_set: DDR3 poll failed on SR entry\n"));
1357 }
1358
1359
1360 if (mode_2t != 0xff) {
1361 t2t = mode_2t;
1362 } else if (timing != MV_DDR_TIM_DEFAULT) {
1363 t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
1364 } else {
1365
1366 cs_num = mv_ddr_cs_num_get();
1367 t2t = (cs_num == 1) ? 0 : 1;
1368 }
1369
1370
1371 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) {
1372
1373 if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) {
1374
1375 CHECK_STATUS(ddr3_tip_if_write
1376 (dev_num, access_type, if_id,
1377 SDRAM_OPEN_PAGES_CTRL_REG, 0x0, 0x3C0));
1378 t2t = 0;
1379 } else {
1380
1381 CHECK_STATUS(ddr3_tip_if_write
1382 (dev_num, access_type, if_id,
1383 SDRAM_OPEN_PAGES_CTRL_REG, 0x3C0, 0x3C0));
1384 }
1385 }
1386 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1387 DUNIT_CTRL_LOW_REG, t2t << 3, 0x3 << 3));
1388
1389
1390 config_func_info[dev_num].tip_set_freq_divider_func(dev_num, if_id,
1391 frequency);
1392
1393
1394 CHECK_STATUS(ddr3_tip_if_write
1395 (dev_num, access_type, if_id, DFS_REG,
1396 (cl_mask_table[cl_value] << 8), 0xf00));
1397 CHECK_STATUS(ddr3_tip_if_write
1398 (dev_num, access_type, if_id, DFS_REG,
1399 (cwl_mask_table[cwl_value] << 12), 0x7000));
1400
1401 t_ckclk = (MEGA / freq);
1402 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get
1403 (speed_bin_index,
1404 SPEED_BIN_TWR), t_ckclk);
1405
1406 CHECK_STATUS(ddr3_tip_if_write
1407 (dev_num, access_type, if_id, DFS_REG,
1408 (twr_mask_table[t_wr] << 16), 0x70000));
1409
1410
1411 if (is_dll_off == 1) {
1412 CHECK_STATUS(ddr3_tip_if_write
1413 (dev_num, access_type, if_id, 0x1874,
1414 g_dic | g_rtt_nom, 0x266));
1415 CHECK_STATUS(ddr3_tip_if_write
1416 (dev_num, access_type, if_id, 0x1884,
1417 g_dic | g_rtt_nom, 0x266));
1418 CHECK_STATUS(ddr3_tip_if_write
1419 (dev_num, access_type, if_id, 0x1894,
1420 g_dic | g_rtt_nom, 0x266));
1421 CHECK_STATUS(ddr3_tip_if_write
1422 (dev_num, access_type, if_id, 0x18a4,
1423 g_dic | g_rtt_nom, 0x266));
1424 }
1425
1426
1427 CHECK_STATUS(ddr3_tip_if_write
1428 (dev_num, access_type, if_id,
1429 SDRAM_CFG_REG, 0, 0x10000000));
1430 mdelay(10);
1431 CHECK_STATUS(ddr3_tip_if_write
1432 (dev_num, access_type, if_id,
1433 SDRAM_CFG_REG, 0x10000000, 0x10000000));
1434
1435
1436 CHECK_STATUS(config_func_info[dev_num].
1437 tip_get_freq_config_info_func(dev_num, frequency,
1438 &freq_config_info));
1439
1440
1441 for (bus_cnt = 0; bus_cnt < octets_per_if_num;
1442 bus_cnt++) {
1443 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
1444 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1445 (dev_num, ACCESS_TYPE_UNICAST,
1446 if_id, bus_cnt, DDR_PHY_DATA,
1447 0x92,
1448 freq_config_info.
1449 bw_per_freq << 8
1450
1451 , 0x700));
1452 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1453 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1454 bus_cnt, DDR_PHY_DATA, 0x94,
1455 freq_config_info.rate_per_freq, 0x7));
1456 }
1457
1458
1459 CHECK_STATUS(ddr3_tip_if_write
1460 (dev_num, access_type, if_id,
1461 DRAM_PHY_CFG_REG, 0,
1462 (0x80000000 | 0x40000000)));
1463 mdelay(100 / (freq / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ)));
1464 CHECK_STATUS(ddr3_tip_if_write
1465 (dev_num, access_type, if_id,
1466 DRAM_PHY_CFG_REG, (0x80000000 | 0x40000000),
1467 (0x80000000 | 0x40000000)));
1468
1469
1470 if (ddr3_tip_if_polling
1471 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x3ff03ff,
1472 0x3ff03ff, PHY_LOCK_STATUS_REG,
1473 MAX_POLLING_ITERATIONS) != MV_OK) {
1474 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1475 ("Freq_set: DDR3 poll failed(1)\n"));
1476 }
1477
1478
1479 CHECK_STATUS(ddr3_tip_if_write
1480 (dev_num, access_type, if_id,
1481 SDRAM_CFG_REG, 0, 0x60000000));
1482 mdelay(10);
1483 CHECK_STATUS(ddr3_tip_if_write
1484 (dev_num, access_type, if_id,
1485 SDRAM_CFG_REG, 0x60000000, 0x60000000));
1486
1487
1488 ddr3_tip_set_timing(dev_num, access_type, if_id, frequency);
1489 if (delay_enable != 0) {
1490 adll_tap = (is_dll_off == 1) ? 1000 : (MEGA / (freq * 64));
1491 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
1492 }
1493
1494
1495 CHECK_STATUS(ddr3_tip_if_write
1496 (dev_num, access_type, if_id, DFS_REG, 0,
1497 0x4));
1498 if (ddr3_tip_if_polling
1499 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x8, DFS_REG,
1500 MAX_POLLING_ITERATIONS) != MV_OK) {
1501 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1502 ("Freq_set: DDR3 poll failed(2)"));
1503 }
1504
1505
1506 CHECK_STATUS(ddr3_tip_if_write
1507 (dev_num, access_type, if_id,
1508 SDRAM_OP_REG, 0x2, 0xf1f));
1509 if (ddr3_tip_if_polling
1510 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f,
1511 SDRAM_OP_REG, MAX_POLLING_ITERATIONS) != MV_OK) {
1512 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1513 ("Freq_set: DDR3 poll failed(3)"));
1514 }
1515
1516
1517 CHECK_STATUS(ddr3_tip_if_write
1518 (dev_num, access_type, if_id, DFS_REG, 0,
1519 0x2));
1520
1521 CHECK_STATUS(ddr3_tip_if_write
1522 (dev_num, access_type, if_id, DUNIT_MMASK_REG,
1523 0x1, 0x1));
1524
1525
1526 val =
1527 ((cl_mask_table[cl_value] & 0x1) << 2) |
1528 ((cl_mask_table[cl_value] & 0xe) << 3);
1529 CHECK_STATUS(ddr3_tip_if_write
1530 (dev_num, access_type, if_id, MR0_REG,
1531 val, (0x7 << 4) | (1 << 2)));
1532
1533 val = (cwl_mask_table[cwl_value] << 3) | g_rtt_wr;
1534
1535
1536
1537
1538
1539
1540
1541 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1542 if_id, MR2_REG,
1543 val, (0x7 << 3) | (0x3 << 9)));
1544
1545
1546 val = ((cl_value - cwl_value + 1) << 4) |
1547 ((cl_value - cwl_value + 6) << 8) |
1548 ((cl_value - 1) << 12) | ((cl_value + 6) << 16);
1549 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1550 if_id, DDR_ODT_TIMING_LOW_REG,
1551 val, 0xffff0));
1552 val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
1553 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1554 if_id, DDR_ODT_TIMING_HIGH_REG,
1555 val, 0xffff));
1556
1557
1558
1559
1560 if (odt_config != 0) {
1561 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, 0xf, 0xf));
1562 }
1563 else {
1564 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG,
1565 0x30f, 0x30f));
1566 }
1567
1568
1569 val = ((cl_mask_table[cl_value] & 0x1) << 2) |
1570 ((cl_mask_table[cl_value] & 0xe) << 3);
1571
1572 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0,
1573 val, (0x7 << 4) | (0x1 << 2)));
1574
1575
1576 val = (cwl_mask_table[cwl_value] << 3) | g_rtt_wr;
1577 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD2,
1578 val, (0x7 << 3) | (0x3 << 9)));
1579
1580 if (mem_mask != 0) {
1581 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1582 if_id,
1583 DUAL_DUNIT_CFG_REG,
1584 1 << 3, 0x8));
1585 }
1586 }
1587
1588 return MV_OK;
1589}
1590
1591
1592
1593
1594static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
1595 u32 if_id, u32 cl_value, u32 cwl_value)
1596{
1597
1598 u32 val = (cl_value - cwl_value + 6);
1599
1600 val = ((cl_value - cwl_value + 1) << 4) | ((val & 0xf) << 8) |
1601 (((cl_value - 1) & 0xf) << 12) |
1602 (((cl_value + 6) & 0xf) << 16) | (((val & 0x10) >> 4) << 21);
1603 val |= (((cl_value - 1) >> 4) << 22) | (((cl_value + 6) >> 4) << 23);
1604
1605 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1606 DDR_ODT_TIMING_LOW_REG, val, 0xffff0));
1607 val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
1608 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1609 DDR_ODT_TIMING_HIGH_REG, val, 0xffff));
1610 if (odt_additional == 1) {
1611 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1612 if_id,
1613 SDRAM_ODT_CTRL_HIGH_REG,
1614 0xf, 0xf));
1615 }
1616
1617
1618 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1619 DUNIT_ODT_CTRL_REG, 0xf, 0xf));
1620
1621 return MV_OK;
1622}
1623
1624
1625
1626
1627static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
1628 u32 if_id, enum mv_ddr_freq frequency)
1629{
1630 u32 t_ckclk = 0, t_ras = 0;
1631 u32 t_rcd = 0, t_rp = 0, t_wr = 0, t_wtr = 0, t_rrd = 0, t_rtp = 0,
1632 t_rfc = 0, t_mod = 0, t_r2r = 0x3, t_r2r_high = 0,
1633 t_r2w_w2r = 0x3, t_r2w_w2r_high = 0x1, t_w2w = 0x3;
1634 u32 refresh_interval_cnt, t_hclk, t_refi, t_faw, t_pd, t_xpdll;
1635 u32 val = 0, page_size = 0, mask = 0;
1636 enum mv_ddr_speed_bin speed_bin_index;
1637 enum mv_ddr_die_capacity memory_size = MV_DDR_DIE_CAP_2GBIT;
1638 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1639 u32 freq = mv_ddr_freq_get(frequency);
1640
1641 speed_bin_index = tm->interface_params[if_id].speed_bin_index;
1642 memory_size = tm->interface_params[if_id].memory_size;
1643 page_size = mv_ddr_page_size_get(tm->interface_params[if_id].bus_width, memory_size);
1644 t_ckclk = (MEGA / freq);
1645
1646 t_hclk = MEGA / (freq / config_func_info[dev_num].tip_get_clock_ratio(frequency));
1647
1648 t_refi = (tm->interface_params[if_id].interface_temp == MV_DDR_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW;
1649 t_refi *= 1000;
1650 refresh_interval_cnt = t_refi / t_hclk;
1651
1652 if (page_size == 1) {
1653 t_faw = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TFAW1K);
1654 t_faw = time_to_nclk(t_faw, t_ckclk);
1655 t_faw = GET_MAX_VALUE(20, t_faw);
1656 } else {
1657 t_faw = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TFAW2K);
1658 t_faw = time_to_nclk(t_faw, t_ckclk);
1659 t_faw = GET_MAX_VALUE(28, t_faw);
1660 }
1661
1662 t_pd = GET_MAX_VALUE(t_ckclk * 3, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TPD));
1663 t_pd = time_to_nclk(t_pd, t_ckclk);
1664
1665 t_xpdll = GET_MAX_VALUE(t_ckclk * 10, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TXPDLL));
1666 t_xpdll = time_to_nclk(t_xpdll, t_ckclk);
1667
1668 t_rrd = (page_size == 1) ? mv_ddr_speed_bin_timing_get(speed_bin_index,
1669 SPEED_BIN_TRRD1K) :
1670 mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRRD2K);
1671 t_rrd = GET_MAX_VALUE(t_ckclk * 4, t_rrd);
1672 t_rtp = GET_MAX_VALUE(t_ckclk * 4, mv_ddr_speed_bin_timing_get(speed_bin_index,
1673 SPEED_BIN_TRTP));
1674 t_mod = GET_MAX_VALUE(t_ckclk * 12, 15000);
1675 t_wtr = GET_MAX_VALUE(t_ckclk * 4, mv_ddr_speed_bin_timing_get(speed_bin_index,
1676 SPEED_BIN_TWTR));
1677 t_ras = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
1678 SPEED_BIN_TRAS),
1679 t_ckclk);
1680 t_rcd = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
1681 SPEED_BIN_TRCD),
1682 t_ckclk);
1683 t_rp = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
1684 SPEED_BIN_TRP),
1685 t_ckclk);
1686 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
1687 SPEED_BIN_TWR),
1688 t_ckclk);
1689 t_wtr = time_to_nclk(t_wtr, t_ckclk);
1690 t_rrd = time_to_nclk(t_rrd, t_ckclk);
1691 t_rtp = time_to_nclk(t_rtp, t_ckclk);
1692 t_rfc = time_to_nclk(mv_ddr_rfc_get(memory_size) * 1000, t_ckclk);
1693 t_mod = time_to_nclk(t_mod, t_ckclk);
1694
1695
1696 val = (((t_ras - 1) & SDRAM_TIMING_LOW_TRAS_MASK) << SDRAM_TIMING_LOW_TRAS_OFFS) |
1697 (((t_rcd - 1) & SDRAM_TIMING_LOW_TRCD_MASK) << SDRAM_TIMING_LOW_TRCD_OFFS) |
1698 (((t_rcd - 1) >> SDRAM_TIMING_LOW_TRCD_OFFS & SDRAM_TIMING_HIGH_TRCD_MASK)
1699 << SDRAM_TIMING_HIGH_TRCD_OFFS) |
1700 (((t_rp - 1) & SDRAM_TIMING_LOW_TRP_MASK) << SDRAM_TIMING_LOW_TRP_OFFS) |
1701 (((t_rp - 1) >> SDRAM_TIMING_LOW_TRP_MASK & SDRAM_TIMING_HIGH_TRP_MASK)
1702 << SDRAM_TIMING_HIGH_TRP_OFFS) |
1703 (((t_wr - 1) & SDRAM_TIMING_LOW_TWR_MASK) << SDRAM_TIMING_LOW_TWR_OFFS) |
1704 (((t_wtr - 1) & SDRAM_TIMING_LOW_TWTR_MASK) << SDRAM_TIMING_LOW_TWTR_OFFS) |
1705 ((((t_ras - 1) >> 4) & SDRAM_TIMING_LOW_TRAS_HIGH_MASK) << SDRAM_TIMING_LOW_TRAS_HIGH_OFFS) |
1706 (((t_rrd - 1) & SDRAM_TIMING_LOW_TRRD_MASK) << SDRAM_TIMING_LOW_TRRD_OFFS) |
1707 (((t_rtp - 1) & SDRAM_TIMING_LOW_TRTP_MASK) << SDRAM_TIMING_LOW_TRTP_OFFS);
1708
1709 mask = (SDRAM_TIMING_LOW_TRAS_MASK << SDRAM_TIMING_LOW_TRAS_OFFS) |
1710 (SDRAM_TIMING_LOW_TRCD_MASK << SDRAM_TIMING_LOW_TRCD_OFFS) |
1711 (SDRAM_TIMING_HIGH_TRCD_MASK << SDRAM_TIMING_HIGH_TRCD_OFFS) |
1712 (SDRAM_TIMING_LOW_TRP_MASK << SDRAM_TIMING_LOW_TRP_OFFS) |
1713 (SDRAM_TIMING_HIGH_TRP_MASK << SDRAM_TIMING_HIGH_TRP_OFFS) |
1714 (SDRAM_TIMING_LOW_TWR_MASK << SDRAM_TIMING_LOW_TWR_OFFS) |
1715 (SDRAM_TIMING_LOW_TWTR_MASK << SDRAM_TIMING_LOW_TWTR_OFFS) |
1716 (SDRAM_TIMING_LOW_TRAS_HIGH_MASK << SDRAM_TIMING_LOW_TRAS_HIGH_OFFS) |
1717 (SDRAM_TIMING_LOW_TRRD_MASK << SDRAM_TIMING_LOW_TRRD_OFFS) |
1718 (SDRAM_TIMING_LOW_TRTP_MASK << SDRAM_TIMING_LOW_TRTP_OFFS);
1719
1720 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1721 SDRAM_TIMING_LOW_REG, val, mask));
1722
1723
1724 val = 0;
1725 mask = 0;
1726
1727 val = (((t_rfc - 1) & SDRAM_TIMING_HIGH_TRFC_MASK) << SDRAM_TIMING_HIGH_TRFC_OFFS) |
1728 ((t_r2r & SDRAM_TIMING_HIGH_TR2R_MASK) << SDRAM_TIMING_HIGH_TR2R_OFFS) |
1729 ((t_r2w_w2r & SDRAM_TIMING_HIGH_TR2W_W2R_MASK) << SDRAM_TIMING_HIGH_TR2W_W2R_OFFS) |
1730 ((t_w2w & SDRAM_TIMING_HIGH_TW2W_MASK) << SDRAM_TIMING_HIGH_TW2W_OFFS) |
1731 ((((t_rfc - 1) >> 7) & SDRAM_TIMING_HIGH_TRFC_HIGH_MASK) << SDRAM_TIMING_HIGH_TRFC_HIGH_OFFS) |
1732 ((t_r2r_high & SDRAM_TIMING_HIGH_TR2R_HIGH_MASK) << SDRAM_TIMING_HIGH_TR2R_HIGH_OFFS) |
1733 ((t_r2w_w2r_high & SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_MASK) << SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_OFFS) |
1734 (((t_mod - 1) & SDRAM_TIMING_HIGH_TMOD_MASK) << SDRAM_TIMING_HIGH_TMOD_OFFS) |
1735 ((((t_mod - 1) >> 4) & SDRAM_TIMING_HIGH_TMOD_HIGH_MASK) << SDRAM_TIMING_HIGH_TMOD_HIGH_OFFS);
1736
1737 mask = (SDRAM_TIMING_HIGH_TRFC_MASK << SDRAM_TIMING_HIGH_TRFC_OFFS) |
1738 (SDRAM_TIMING_HIGH_TR2R_MASK << SDRAM_TIMING_HIGH_TR2R_OFFS) |
1739 (SDRAM_TIMING_HIGH_TR2W_W2R_MASK << SDRAM_TIMING_HIGH_TR2W_W2R_OFFS) |
1740 (SDRAM_TIMING_HIGH_TW2W_MASK << SDRAM_TIMING_HIGH_TW2W_OFFS) |
1741 (SDRAM_TIMING_HIGH_TRFC_HIGH_MASK << SDRAM_TIMING_HIGH_TRFC_HIGH_OFFS) |
1742 (SDRAM_TIMING_HIGH_TR2R_HIGH_MASK << SDRAM_TIMING_HIGH_TR2R_HIGH_OFFS) |
1743 (SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_MASK << SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_OFFS) |
1744 (SDRAM_TIMING_HIGH_TMOD_MASK << SDRAM_TIMING_HIGH_TMOD_OFFS) |
1745 (SDRAM_TIMING_HIGH_TMOD_HIGH_MASK << SDRAM_TIMING_HIGH_TMOD_HIGH_OFFS);
1746
1747 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1748 SDRAM_TIMING_HIGH_REG, val, mask));
1749
1750 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1751 SDRAM_CFG_REG,
1752 refresh_interval_cnt << REFRESH_OFFS,
1753 REFRESH_MASK << REFRESH_OFFS));
1754 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1755 SDRAM_ADDR_CTRL_REG, (t_faw - 1) << T_FAW_OFFS,
1756 T_FAW_MASK << T_FAW_OFFS));
1757
1758 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DDR_TIMING_REG,
1759 (t_pd - 1) << DDR_TIMING_TPD_OFFS |
1760 (t_xpdll - 1) << DDR_TIMING_TXPDLL_OFFS,
1761 DDR_TIMING_TPD_MASK << DDR_TIMING_TPD_OFFS |
1762 DDR_TIMING_TXPDLL_MASK << DDR_TIMING_TXPDLL_OFFS));
1763
1764
1765 return MV_OK;
1766}
1767
1768
1769
1770
1771
1772int ddr3_tip_write_cs_result(u32 dev_num, u32 offset)
1773{
1774 u32 if_id, bus_num, cs_bitmask, data_val, cs_num;
1775 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1776 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1777
1778 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1779 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1780 for (bus_num = 0; bus_num < octets_per_if_num;
1781 bus_num++) {
1782 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num);
1783 cs_bitmask =
1784 tm->interface_params[if_id].
1785 as_bus_params[bus_num].cs_bitmask;
1786 if (cs_bitmask != effective_cs) {
1787 cs_num = GET_CS_FROM_MASK(cs_bitmask);
1788 ddr3_tip_bus_read(dev_num, if_id,
1789 ACCESS_TYPE_UNICAST, bus_num,
1790 DDR_PHY_DATA,
1791 offset +
1792 (effective_cs * 0x4),
1793 &data_val);
1794 ddr3_tip_bus_write(dev_num,
1795 ACCESS_TYPE_UNICAST,
1796 if_id,
1797 ACCESS_TYPE_UNICAST,
1798 bus_num, DDR_PHY_DATA,
1799 offset +
1800 (cs_num * 0x4),
1801 data_val);
1802 }
1803 }
1804 }
1805
1806 return MV_OK;
1807}
1808
1809
1810
1811
1812int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask)
1813{
1814 u32 if_id;
1815 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1816
1817 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1818 PARAM_NOT_CARE, mr_data[mr_num].reg_addr, data, mask));
1819 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1820 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1821 CHECK_STATUS(ddr3_tip_if_write
1822 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1823 SDRAM_OP_REG,
1824 (cs_mask_arr[if_id] << 8) | mr_data[mr_num].cmd, 0xf1f));
1825 }
1826
1827 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1828 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1829 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0,
1830 0x1f, SDRAM_OP_REG,
1831 MAX_POLLING_ITERATIONS) != MV_OK) {
1832 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1833 ("write_mrs_cmd: Poll cmd fail"));
1834 }
1835 }
1836
1837 return MV_OK;
1838}
1839
1840
1841
1842
1843int ddr3_tip_reset_fifo_ptr(u32 dev_num)
1844{
1845 u32 if_id = 0;
1846
1847
1848 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1849 if_id, 0x15c8, 0, 0xff000000));
1850
1851
1852
1853
1854 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1855 if_id, TRAINING_SW_2_REG,
1856 0x1, 0x9));
1857
1858 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1859 if_id, 0x15b0,
1860 0x80000000, 0x80000000));
1861
1862 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1863 if_id, 0x1400, 0, 0x40000000));
1864
1865 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1866 if_id, 0x1400,
1867 0x40000000, 0x40000000));
1868
1869 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1870 if_id, TRAINING_SW_2_REG,
1871 0x8, 0x9));
1872
1873 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1874 if_id, 0x15b4, 0x10000, 0x10000));
1875
1876 return MV_OK;
1877}
1878
1879
1880
1881
1882int ddr3_tip_ddr3_reset_phy_regs(u32 dev_num)
1883{
1884 u32 if_id, phy_id, cs;
1885 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1886 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1887
1888 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1889 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1890 for (phy_id = 0; phy_id < octets_per_if_num;
1891 phy_id++) {
1892 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id);
1893 CHECK_STATUS(ddr3_tip_bus_write
1894 (dev_num, ACCESS_TYPE_UNICAST,
1895 if_id, ACCESS_TYPE_UNICAST,
1896 phy_id, DDR_PHY_DATA,
1897 WL_PHY_REG(effective_cs),
1898 phy_reg0_val));
1899 CHECK_STATUS(ddr3_tip_bus_write
1900 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1901 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1902 RL_PHY_REG(effective_cs),
1903 phy_reg2_val));
1904 CHECK_STATUS(ddr3_tip_bus_write
1905 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1906 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1907 CRX_PHY_REG(effective_cs), phy_reg3_val));
1908 CHECK_STATUS(ddr3_tip_bus_write
1909 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1910 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1911 CTX_PHY_REG(effective_cs), phy_reg1_val));
1912 CHECK_STATUS(ddr3_tip_bus_write
1913 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1914 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1915 PBS_TX_BCAST_PHY_REG(effective_cs), 0x0));
1916 CHECK_STATUS(ddr3_tip_bus_write
1917 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1918 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1919 PBS_RX_BCAST_PHY_REG(effective_cs), 0));
1920 CHECK_STATUS(ddr3_tip_bus_write
1921 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1922 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1923 PBS_TX_PHY_REG(effective_cs, DQSP_PAD), 0));
1924 CHECK_STATUS(ddr3_tip_bus_write
1925 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1926 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1927 PBS_RX_PHY_REG(effective_cs, DQSP_PAD), 0));
1928 CHECK_STATUS(ddr3_tip_bus_write
1929 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1930 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1931 PBS_TX_PHY_REG(effective_cs, DQSN_PAD), 0));
1932 CHECK_STATUS(ddr3_tip_bus_write
1933 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1934 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1935 PBS_RX_PHY_REG(effective_cs, DQSN_PAD), 0));
1936 }
1937 }
1938
1939
1940 for (cs = 0; cs < MAX_CS_NUM; cs++) {
1941
1942 CHECK_STATUS(ddr3_tip_bus_write
1943 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1944 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1945 DDR_PHY_DATA, VREF_BCAST_PHY_REG(cs), 63));
1946 }
1947
1948 return MV_OK;
1949}
1950
1951
1952
1953
1954int ddr3_tip_restore_dunit_regs(u32 dev_num)
1955{
1956 u32 index_cnt;
1957
1958 mv_ddr_set_calib_controller();
1959
1960 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1961 PARAM_NOT_CARE, MAIN_PADS_CAL_MACH_CTRL_REG,
1962 0x1, 0x1));
1963 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1964 PARAM_NOT_CARE, MAIN_PADS_CAL_MACH_CTRL_REG,
1965 calibration_update_control << 3,
1966 0x3 << 3));
1967 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1968 PARAM_NOT_CARE,
1969 ODPG_WR_RD_MODE_ENA_REG,
1970 0xffff, MASK_ALL_BITS));
1971
1972 for (index_cnt = 0; index_cnt < ARRAY_SIZE(odpg_default_value);
1973 index_cnt++) {
1974 CHECK_STATUS(ddr3_tip_if_write
1975 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1976 odpg_default_value[index_cnt].reg_addr,
1977 odpg_default_value[index_cnt].reg_data,
1978 odpg_default_value[index_cnt].reg_mask));
1979 }
1980
1981 return MV_OK;
1982}
1983
1984int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2)
1985{
1986 u32 if_id, phy_id;
1987 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1988 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1989
1990 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1991 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1992 for (phy_id = 0; phy_id < octets_per_if_num; phy_id++) {
1993 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id);
1994 CHECK_STATUS(ddr3_tip_bus_write
1995 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1996 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
1997 CTX_PHY_REG(effective_cs), reg_val1));
1998 CHECK_STATUS(ddr3_tip_bus_write
1999 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2000 ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2001 PBS_TX_BCAST_PHY_REG(effective_cs), reg_val2));
2002 }
2003 }
2004
2005 return MV_OK;
2006}
2007
2008
2009
2010
2011static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
2012{
2013
2014#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
2015 struct init_cntr_param init_cntr_prm;
2016#endif
2017 int ret = MV_OK;
2018 int adll_bypass_flag = 0;
2019 u32 if_id;
2020 unsigned int max_cs = mv_ddr_cs_num_get();
2021 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2022 enum mv_ddr_freq freq = tm->interface_params[0].memory_freq;
2023 unsigned int *freq_tbl = mv_ddr_freq_tbl_get();
2024
2025#ifdef DDR_VIEWER_TOOL
2026 if (debug_training == DEBUG_LEVEL_TRACE) {
2027 CHECK_STATUS(print_device_info((u8)dev_num));
2028 }
2029#endif
2030
2031 ddr3_tip_validate_algo_components(dev_num);
2032
2033 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2034 CHECK_STATUS(ddr3_tip_ddr3_reset_phy_regs(dev_num));
2035 }
2036
2037 effective_cs = 0;
2038
2039 freq_tbl[MV_DDR_FREQ_LOW_FREQ] = dfs_low_freq;
2040
2041 if (is_pll_before_init != 0) {
2042 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
2043 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
2044 config_func_info[dev_num].tip_set_freq_divider_func(
2045 (u8)dev_num, if_id, freq);
2046 }
2047 }
2048
2049
2050#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
2051 if (is_adll_calib_before_init != 0) {
2052 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2053 ("with adll calib before init\n"));
2054 adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
2055 }
2056
2057 if (is_reg_dump != 0) {
2058 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2059 ("Dump before init controller\n"));
2060 ddr3_tip_reg_dump(dev_num);
2061 }
2062
2063 if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) {
2064 training_stage = INIT_CONTROLLER;
2065 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2066 ("INIT_CONTROLLER_MASK_BIT\n"));
2067 init_cntr_prm.do_mrs_phy = 1;
2068 init_cntr_prm.is_ctrl64_bit = 0;
2069 init_cntr_prm.init_phy = 1;
2070 init_cntr_prm.msys_init = 0;
2071 ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm);
2072 if (is_reg_dump != 0)
2073 ddr3_tip_reg_dump(dev_num);
2074 if (ret != MV_OK) {
2075 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2076 ("hws_ddr3_tip_init_controller failure\n"));
2077 if (debug_mode == 0)
2078 return MV_FAIL;
2079 }
2080 }
2081#endif
2082
2083 ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
2084 if (ret != MV_OK) {
2085 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2086 ("adll_calibration failure\n"));
2087 if (debug_mode == 0)
2088 return MV_FAIL;
2089 }
2090
2091 if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) {
2092 training_stage = SET_LOW_FREQ;
2093
2094 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2095 ddr3_tip_adll_regs_bypass(dev_num, 0, 0x1f);
2096 adll_bypass_flag = 1;
2097 }
2098 effective_cs = 0;
2099
2100 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2101 ("SET_LOW_FREQ_MASK_BIT %d\n",
2102 freq_tbl[low_freq]));
2103 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2104 PARAM_NOT_CARE, low_freq);
2105 if (is_reg_dump != 0)
2106 ddr3_tip_reg_dump(dev_num);
2107 if (ret != MV_OK) {
2108 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2109 ("ddr3_tip_freq_set failure\n"));
2110 if (debug_mode == 0)
2111 return MV_FAIL;
2112 }
2113 }
2114
2115 if (mask_tune_func & WRITE_LEVELING_LF_MASK_BIT) {
2116 training_stage = WRITE_LEVELING_LF;
2117 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2118 ("WRITE_LEVELING_LF_MASK_BIT\n"));
2119 ret = ddr3_tip_dynamic_write_leveling(dev_num, 1);
2120 if (is_reg_dump != 0)
2121 ddr3_tip_reg_dump(dev_num);
2122 if (ret != MV_OK) {
2123 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2124 ("ddr3_tip_dynamic_write_leveling LF failure\n"));
2125 if (debug_mode == 0)
2126 return MV_FAIL;
2127 }
2128 }
2129
2130 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2131 if (mask_tune_func & LOAD_PATTERN_MASK_BIT) {
2132 training_stage = LOAD_PATTERN;
2133 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2134 ("LOAD_PATTERN_MASK_BIT #%d\n",
2135 effective_cs));
2136 ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2137 if (is_reg_dump != 0)
2138 ddr3_tip_reg_dump(dev_num);
2139 if (ret != MV_OK) {
2140 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2141 ("ddr3_tip_load_all_pattern_to_mem failure CS #%d\n",
2142 effective_cs));
2143 if (debug_mode == 0)
2144 return MV_FAIL;
2145 }
2146 }
2147 }
2148
2149 if (adll_bypass_flag == 1) {
2150 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2151 ddr3_tip_adll_regs_bypass(dev_num, phy_reg1_val, 0);
2152 adll_bypass_flag = 0;
2153 }
2154 }
2155
2156
2157 effective_cs = 0;
2158
2159 if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {
2160 training_stage = SET_MEDIUM_FREQ;
2161 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2162 ("SET_MEDIUM_FREQ_MASK_BIT %d\n",
2163 freq_tbl[medium_freq]));
2164 ret =
2165 ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2166 PARAM_NOT_CARE, medium_freq);
2167 if (is_reg_dump != 0)
2168 ddr3_tip_reg_dump(dev_num);
2169 if (ret != MV_OK) {
2170 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2171 ("ddr3_tip_freq_set failure\n"));
2172 if (debug_mode == 0)
2173 return MV_FAIL;
2174 }
2175 }
2176
2177 if (mask_tune_func & WRITE_LEVELING_MASK_BIT) {
2178 training_stage = WRITE_LEVELING;
2179 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2180 ("WRITE_LEVELING_MASK_BIT\n"));
2181 if ((rl_mid_freq_wa == 0) || (freq_tbl[medium_freq] == 533)) {
2182 ret = ddr3_tip_dynamic_write_leveling(dev_num, 0);
2183 } else {
2184
2185 ret = ddr3_tip_legacy_dynamic_write_leveling(dev_num);
2186 }
2187
2188 if (is_reg_dump != 0)
2189 ddr3_tip_reg_dump(dev_num);
2190 if (ret != MV_OK) {
2191 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2192 ("ddr3_tip_dynamic_write_leveling failure\n"));
2193 if (debug_mode == 0)
2194 return MV_FAIL;
2195 }
2196 }
2197
2198 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2199 if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) {
2200 training_stage = LOAD_PATTERN_2;
2201 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2202 ("LOAD_PATTERN_2_MASK_BIT CS #%d\n",
2203 effective_cs));
2204 ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2205 if (is_reg_dump != 0)
2206 ddr3_tip_reg_dump(dev_num);
2207 if (ret != MV_OK) {
2208 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2209 ("ddr3_tip_load_all_pattern_to_mem failure CS #%d\n",
2210 effective_cs));
2211 if (debug_mode == 0)
2212 return MV_FAIL;
2213 }
2214 }
2215 }
2216
2217 effective_cs = 0;
2218
2219 if (mask_tune_func & READ_LEVELING_MASK_BIT) {
2220 training_stage = READ_LEVELING;
2221 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2222 ("READ_LEVELING_MASK_BIT\n"));
2223 if ((rl_mid_freq_wa == 0) || (freq_tbl[medium_freq] == 533)) {
2224 ret = ddr3_tip_dynamic_read_leveling(dev_num, medium_freq);
2225 } else {
2226
2227 ret = ddr3_tip_legacy_dynamic_read_leveling(dev_num);
2228 }
2229
2230 if (is_reg_dump != 0)
2231 ddr3_tip_reg_dump(dev_num);
2232 if (ret != MV_OK) {
2233 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2234 ("ddr3_tip_dynamic_read_leveling failure\n"));
2235 if (debug_mode == 0)
2236 return MV_FAIL;
2237 }
2238 }
2239
2240 if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) {
2241 training_stage = WRITE_LEVELING_SUPP;
2242 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2243 ("WRITE_LEVELING_SUPP_MASK_BIT\n"));
2244 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
2245 if (is_reg_dump != 0)
2246 ddr3_tip_reg_dump(dev_num);
2247 if (ret != MV_OK) {
2248 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2249 ("ddr3_tip_dynamic_write_leveling_supp failure\n"));
2250 if (debug_mode == 0)
2251 return MV_FAIL;
2252 }
2253 }
2254
2255 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2256 if (mask_tune_func & PBS_RX_MASK_BIT) {
2257 training_stage = PBS_RX;
2258 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2259 ("PBS_RX_MASK_BIT CS #%d\n",
2260 effective_cs));
2261 ret = ddr3_tip_pbs_rx(dev_num);
2262 if (is_reg_dump != 0)
2263 ddr3_tip_reg_dump(dev_num);
2264 if (ret != MV_OK) {
2265 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2266 ("ddr3_tip_pbs_rx failure CS #%d\n",
2267 effective_cs));
2268 if (debug_mode == 0)
2269 return MV_FAIL;
2270 }
2271 }
2272 }
2273
2274 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2275 if (mask_tune_func & PBS_TX_MASK_BIT) {
2276 training_stage = PBS_TX;
2277 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2278 ("PBS_TX_MASK_BIT CS #%d\n",
2279 effective_cs));
2280 ret = ddr3_tip_pbs_tx(dev_num);
2281 if (is_reg_dump != 0)
2282 ddr3_tip_reg_dump(dev_num);
2283 if (ret != MV_OK) {
2284 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2285 ("ddr3_tip_pbs_tx failure CS #%d\n",
2286 effective_cs));
2287 if (debug_mode == 0)
2288 return MV_FAIL;
2289 }
2290 }
2291 }
2292
2293 effective_cs = 0;
2294
2295 if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) {
2296 training_stage = SET_TARGET_FREQ;
2297 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2298 ("SET_TARGET_FREQ_MASK_BIT %d\n",
2299 freq_tbl[tm->
2300 interface_params[first_active_if].
2301 memory_freq]));
2302 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2303 PARAM_NOT_CARE,
2304 tm->interface_params[first_active_if].
2305 memory_freq);
2306 if (is_reg_dump != 0)
2307 ddr3_tip_reg_dump(dev_num);
2308 if (ret != MV_OK) {
2309 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2310 ("ddr3_tip_freq_set failure\n"));
2311 if (debug_mode == 0)
2312 return MV_FAIL;
2313 }
2314 }
2315
2316 if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) {
2317 training_stage = WRITE_LEVELING_TF;
2318 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2319 ("WRITE_LEVELING_TF_MASK_BIT\n"));
2320 ret = ddr3_tip_dynamic_write_leveling(dev_num, 0);
2321 if (is_reg_dump != 0)
2322 ddr3_tip_reg_dump(dev_num);
2323 if (ret != MV_OK) {
2324 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2325 ("ddr3_tip_dynamic_write_leveling TF failure\n"));
2326 if (debug_mode == 0)
2327 return MV_FAIL;
2328 }
2329 }
2330
2331 if (mask_tune_func & LOAD_PATTERN_HIGH_MASK_BIT) {
2332 training_stage = LOAD_PATTERN_HIGH;
2333 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("LOAD_PATTERN_HIGH\n"));
2334 ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2335 if (is_reg_dump != 0)
2336 ddr3_tip_reg_dump(dev_num);
2337 if (ret != MV_OK) {
2338 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2339 ("ddr3_tip_load_all_pattern_to_mem failure\n"));
2340 if (debug_mode == 0)
2341 return MV_FAIL;
2342 }
2343 }
2344
2345 if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {
2346 training_stage = READ_LEVELING_TF;
2347 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2348 ("READ_LEVELING_TF_MASK_BIT\n"));
2349 ret = ddr3_tip_dynamic_read_leveling(dev_num, tm->
2350 interface_params[first_active_if].
2351 memory_freq);
2352 if (is_reg_dump != 0)
2353 ddr3_tip_reg_dump(dev_num);
2354 if (ret != MV_OK) {
2355 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2356 ("ddr3_tip_dynamic_read_leveling TF failure\n"));
2357 if (debug_mode == 0)
2358 return MV_FAIL;
2359 }
2360 }
2361
2362 if (mask_tune_func & RL_DQS_BURST_MASK_BIT) {
2363 training_stage = READ_LEVELING_TF;
2364 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2365 ("RL_DQS_BURST_MASK_BIT\n"));
2366 ret = mv_ddr_rl_dqs_burst(0, 0, tm->interface_params[0].memory_freq);
2367 if (is_reg_dump != 0)
2368 ddr3_tip_reg_dump(dev_num);
2369 if (ret != MV_OK) {
2370 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2371 ("mv_ddr_rl_dqs_burst TF failure\n"));
2372 if (debug_mode == 0)
2373 return MV_FAIL;
2374 }
2375 }
2376
2377 if (mask_tune_func & DM_PBS_TX_MASK_BIT) {
2378 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("DM_PBS_TX_MASK_BIT\n"));
2379 }
2380
2381 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2382 if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) {
2383 training_stage = VREF_CALIBRATION;
2384 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("VREF\n"));
2385 ret = ddr3_tip_vref(dev_num);
2386 if (is_reg_dump != 0) {
2387 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2388 ("VREF Dump\n"));
2389 ddr3_tip_reg_dump(dev_num);
2390 }
2391 if (ret != MV_OK) {
2392 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2393 ("ddr3_tip_vref failure\n"));
2394 if (debug_mode == 0)
2395 return MV_FAIL;
2396 }
2397 }
2398 }
2399
2400 effective_cs = 0;
2401
2402 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2403 if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) {
2404 training_stage = CENTRALIZATION_RX;
2405 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2406 ("CENTRALIZATION_RX_MASK_BIT CS #%d\n",
2407 effective_cs));
2408 ret = ddr3_tip_centralization_rx(dev_num);
2409 if (is_reg_dump != 0)
2410 ddr3_tip_reg_dump(dev_num);
2411 if (ret != MV_OK) {
2412 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2413 ("ddr3_tip_centralization_rx failure CS #%d\n",
2414 effective_cs));
2415 if (debug_mode == 0)
2416 return MV_FAIL;
2417 }
2418 }
2419 }
2420
2421 effective_cs = 0;
2422
2423 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2424 if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {
2425 training_stage = WRITE_LEVELING_SUPP_TF;
2426 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2427 ("WRITE_LEVELING_SUPP_TF_MASK_BIT CS #%d\n",
2428 effective_cs));
2429 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
2430 if (is_reg_dump != 0)
2431 ddr3_tip_reg_dump(dev_num);
2432 if (ret != MV_OK) {
2433 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2434 ("ddr3_tip_dynamic_write_leveling_supp TF failure CS #%d\n",
2435 effective_cs));
2436 if (debug_mode == 0)
2437 return MV_FAIL;
2438 }
2439 }
2440 }
2441
2442 effective_cs = 0;
2443
2444
2445 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2446 if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) {
2447 training_stage = CENTRALIZATION_TX;
2448 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2449 ("CENTRALIZATION_TX_MASK_BIT CS #%d\n",
2450 effective_cs));
2451 ret = ddr3_tip_centralization_tx(dev_num);
2452 if (is_reg_dump != 0)
2453 ddr3_tip_reg_dump(dev_num);
2454 if (ret != MV_OK) {
2455 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2456 ("ddr3_tip_centralization_tx failure CS #%d\n",
2457 effective_cs));
2458 if (debug_mode == 0)
2459 return MV_FAIL;
2460 }
2461 }
2462 }
2463
2464 effective_cs = 0;
2465
2466 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("restore registers to default\n"));
2467
2468 CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
2469
2470 if (is_reg_dump != 0)
2471 ddr3_tip_reg_dump(dev_num);
2472
2473 return MV_OK;
2474}
2475
2476
2477
2478
2479static int ddr3_tip_ddr3_auto_tune(u32 dev_num)
2480{
2481 int status;
2482 u32 if_id, stage;
2483 int is_if_fail = 0, is_auto_tune_fail = 0;
2484
2485 training_stage = INIT_CONTROLLER;
2486
2487 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2488 for (stage = 0; stage < MAX_STAGE_LIMIT; stage++)
2489 training_result[stage][if_id] = NO_TEST_DONE;
2490 }
2491
2492 status = ddr3_tip_ddr3_training_main_flow(dev_num);
2493
2494
2495 if (xsb_validate_type != 0) {
2496 run_xsb_test(dev_num, xsb_validation_base_address, 1, 1,
2497 0x1024);
2498 }
2499
2500 if (is_reg_dump != 0)
2501 ddr3_tip_reg_dump(dev_num);
2502
2503
2504 CHECK_STATUS(ddr3_tip_print_log(dev_num, window_mem_addr));
2505
2506#ifndef EXCLUDE_DEBUG_PRINTS
2507 if (status != MV_OK) {
2508 CHECK_STATUS(ddr3_tip_print_stability_log(dev_num));
2509 }
2510#endif
2511
2512 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2513 is_if_fail = 0;
2514 for (stage = 0; stage < MAX_STAGE_LIMIT; stage++) {
2515 if (training_result[stage][if_id] == TEST_FAILED)
2516 is_if_fail = 1;
2517 }
2518 if (is_if_fail == 1) {
2519 is_auto_tune_fail = 1;
2520 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2521 ("Auto Tune failed for IF %d\n",
2522 if_id));
2523 }
2524 }
2525
2526 if (((status == MV_FAIL) && (is_auto_tune_fail == 0)) ||
2527 ((status == MV_OK) && (is_auto_tune_fail == 1))) {
2528
2529
2530
2531
2532
2533 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2534 ("Warning: Algorithm return value and Result DB"
2535 "are not synced (status 0x%x result DB %d)\n",
2536 status, is_auto_tune_fail));
2537 }
2538
2539 if ((status != MV_OK) || (is_auto_tune_fail == 1))
2540 return MV_FAIL;
2541 else
2542 return MV_OK;
2543}
2544
2545
2546
2547
2548int ddr3_tip_enable_init_sequence(u32 dev_num)
2549{
2550 int is_fail = 0;
2551 u32 if_id = 0, mem_mask = 0, bus_index = 0;
2552 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
2553 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2554
2555
2556 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, 0,
2557 SDRAM_INIT_CTRL_REG, 0x1, 0x1));
2558
2559 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2560 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
2561
2562 if (ddr3_tip_if_polling
2563 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1,
2564 SDRAM_INIT_CTRL_REG,
2565 MAX_POLLING_ITERATIONS) != MV_OK) {
2566 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2567 ("polling failed IF %d\n",
2568 if_id));
2569 is_fail = 1;
2570 continue;
2571 }
2572
2573 mem_mask = 0;
2574 for (bus_index = 0; bus_index < octets_per_if_num;
2575 bus_index++) {
2576 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index);
2577 mem_mask |=
2578 tm->interface_params[if_id].
2579 as_bus_params[bus_index].mirror_enable_bitmask;
2580 }
2581
2582 if (mem_mask != 0) {
2583
2584 CHECK_STATUS(ddr3_tip_if_write
2585 (dev_num, ACCESS_TYPE_MULTICAST,
2586 if_id, DUAL_DUNIT_CFG_REG, 1 << 3,
2587 1 << 3));
2588 }
2589 }
2590
2591 return (is_fail == 0) ? MV_OK : MV_FAIL;
2592}
2593
2594int ddr3_tip_register_dq_table(u32 dev_num, u32 *table)
2595{
2596 dq_map_table = table;
2597
2598 return MV_OK;
2599}
2600
2601
2602
2603
2604int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode)
2605{
2606 u32 bit_start = 0, bit_end = 0, bit_id;
2607
2608 if (read_mode == RESULT_PER_BIT) {
2609 bit_start = 0;
2610 bit_end = BUS_WIDTH_IN_BITS - 1;
2611 } else {
2612 bit_start = 0;
2613 bit_end = 0;
2614 }
2615
2616 for (bit_id = bit_start; bit_id <= bit_end; bit_id++) {
2617 if (GET_LOCK_RESULT(pup_buf[bit_id]) == 0)
2618 return 0;
2619 }
2620
2621 return 1;
2622}
2623
2624
2625
2626
2627u8 ddr3_tip_get_buf_min(u8 *buf_ptr)
2628{
2629 u8 min_val = 0xff;
2630 u8 cnt = 0;
2631
2632 for (cnt = 0; cnt < BUS_WIDTH_IN_BITS; cnt++) {
2633 if (buf_ptr[cnt] < min_val)
2634 min_val = buf_ptr[cnt];
2635 }
2636
2637 return min_val;
2638}
2639
2640
2641
2642
2643u8 ddr3_tip_get_buf_max(u8 *buf_ptr)
2644{
2645 u8 max_val = 0;
2646 u8 cnt = 0;
2647
2648 for (cnt = 0; cnt < BUS_WIDTH_IN_BITS; cnt++) {
2649 if (buf_ptr[cnt] > max_val)
2650 max_val = buf_ptr[cnt];
2651 }
2652
2653 return max_val;
2654}
2655
2656
2657
2658
2659
2660
2661u32 hws_ddr3_get_bus_width(void)
2662{
2663 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2664
2665 return (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) ==
2666 1) ? 16 : 32;
2667}
2668
2669u32 hws_ddr3_get_device_width(u32 if_id)
2670{
2671 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2672
2673 return (tm->interface_params[if_id].bus_width ==
2674 MV_DDR_DEV_WIDTH_8BIT) ? 8 : 16;
2675}
2676
2677u32 hws_ddr3_get_device_size(u32 if_id)
2678{
2679 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2680
2681 if (tm->interface_params[if_id].memory_size >=
2682 MV_DDR_DIE_CAP_LAST) {
2683 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2684 ("Error: Wrong device size of Cs: %d",
2685 tm->interface_params[if_id].memory_size));
2686 return 0;
2687 } else {
2688 return 1 << tm->interface_params[if_id].memory_size;
2689 }
2690}
2691
2692int hws_ddr3_calc_mem_cs_size(u32 if_id, u32 cs, u32 *cs_size)
2693{
2694 u32 cs_mem_size, dev_size;
2695
2696 dev_size = hws_ddr3_get_device_size(if_id);
2697 if (dev_size != 0) {
2698 cs_mem_size = ((hws_ddr3_get_bus_width() /
2699 hws_ddr3_get_device_width(if_id)) * dev_size);
2700
2701
2702
2703 if (cs_mem_size == 2) {
2704 *cs_size = _128M;
2705 } else if (cs_mem_size == 4) {
2706 *cs_size = _256M;
2707 } else if (cs_mem_size == 8) {
2708 *cs_size = _512M;
2709 } else if (cs_mem_size == 16) {
2710 *cs_size = _1G;
2711 } else if (cs_mem_size == 32) {
2712 *cs_size = _2G;
2713 } else {
2714 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2715 ("Error: Wrong Memory size of Cs: %d", cs));
2716 return MV_FAIL;
2717 }
2718 return MV_OK;
2719 } else {
2720 return MV_FAIL;
2721 }
2722}
2723
2724int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr)
2725{
2726 u32 cs_mem_size = 0;
2727#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
2728 u32 physical_mem_size;
2729 u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
2730#endif
2731
2732 if (hws_ddr3_calc_mem_cs_size(if_id, cs, &cs_mem_size) != MV_OK)
2733 return MV_FAIL;
2734
2735#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
2736 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2737
2738
2739
2740
2741
2742 physical_mem_size = mem_size[tm->interface_params[0].memory_size];
2743
2744 if (hws_ddr3_get_device_width(cs) == 16) {
2745
2746
2747
2748
2749 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE * 2;
2750 }
2751
2752 if (physical_mem_size > max_mem_size) {
2753 cs_mem_size = max_mem_size *
2754 (hws_ddr3_get_bus_width() /
2755 hws_ddr3_get_device_width(if_id));
2756 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2757 ("Updated Physical Mem size is from 0x%x to %x\n",
2758 physical_mem_size,
2759 DEVICE_MAX_DRAM_ADDRESS_SIZE));
2760 }
2761#endif
2762
2763
2764 *cs_base_addr = ((cs_mem_size) * cs) & 0xffff0000;
2765
2766 return MV_OK;
2767}
2768
2769
2770enum {
2771 MISL_PHY_DRV_OHM_30 = 0xf,
2772 MISL_PHY_DRV_OHM_48 = 0xa,
2773 MISL_PHY_DRV_OHM_80 = 0x6,
2774 MISL_PHY_DRV_OHM_120 = 0x4
2775};
2776
2777enum {
2778 MISL_PHY_ODT_OHM_60 = 0x8,
2779 MISL_PHY_ODT_OHM_80 = 0x6,
2780 MISL_PHY_ODT_OHM_120 = 0x4,
2781 MISL_PHY_ODT_OHM_240 = 0x2
2782};
2783
2784static unsigned int mv_ddr_misl_phy_drv_calc(unsigned int cfg)
2785{
2786 unsigned int val;
2787
2788 switch (cfg) {
2789 case MV_DDR_OHM_30:
2790 val = MISL_PHY_DRV_OHM_30;
2791 break;
2792 case MV_DDR_OHM_48:
2793 val = MISL_PHY_DRV_OHM_48;
2794 break;
2795 case MV_DDR_OHM_80:
2796 val = MISL_PHY_DRV_OHM_80;
2797 break;
2798 case MV_DDR_OHM_120:
2799 val = MISL_PHY_DRV_OHM_120;
2800 break;
2801 default:
2802 val = PARAM_UNDEFINED;
2803 }
2804
2805 return val;
2806}
2807
2808static unsigned int mv_ddr_misl_phy_odt_calc(unsigned int cfg)
2809{
2810 unsigned int val;
2811
2812 switch (cfg) {
2813 case MV_DDR_OHM_60:
2814 val = MISL_PHY_ODT_OHM_60;
2815 break;
2816 case MV_DDR_OHM_80:
2817 val = MISL_PHY_ODT_OHM_80;
2818 break;
2819 case MV_DDR_OHM_120:
2820 val = MISL_PHY_ODT_OHM_120;
2821 break;
2822 case MV_DDR_OHM_240:
2823 val = MISL_PHY_ODT_OHM_240;
2824 break;
2825 default:
2826 val = PARAM_UNDEFINED;
2827 }
2828
2829 return val;
2830}
2831
2832unsigned int mv_ddr_misl_phy_drv_data_p_get(void)
2833{
2834 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2835 unsigned int drv_data_p = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_data_p);
2836
2837 if (drv_data_p == PARAM_UNDEFINED)
2838 printf("error: %s: unsupported drv_data_p parameter found\n", __func__);
2839
2840 return drv_data_p;
2841}
2842
2843unsigned int mv_ddr_misl_phy_drv_data_n_get(void)
2844{
2845 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2846 unsigned int drv_data_n = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_data_n);
2847
2848 if (drv_data_n == PARAM_UNDEFINED)
2849 printf("error: %s: unsupported drv_data_n parameter found\n", __func__);
2850
2851 return drv_data_n;
2852}
2853
2854unsigned int mv_ddr_misl_phy_drv_ctrl_p_get(void)
2855{
2856 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2857 unsigned int drv_ctrl_p = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_ctrl_p);
2858
2859 if (drv_ctrl_p == PARAM_UNDEFINED)
2860 printf("error: %s: unsupported drv_ctrl_p parameter found\n", __func__);
2861
2862 return drv_ctrl_p;
2863}
2864
2865unsigned int mv_ddr_misl_phy_drv_ctrl_n_get(void)
2866{
2867 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2868 unsigned int drv_ctrl_n = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_ctrl_n);
2869
2870 if (drv_ctrl_n == PARAM_UNDEFINED)
2871 printf("error: %s: unsupported drv_ctrl_n parameter found\n", __func__);
2872
2873 return drv_ctrl_n;
2874}
2875
2876unsigned int mv_ddr_misl_phy_odt_p_get(void)
2877{
2878 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2879 unsigned int cs_num = mv_ddr_cs_num_get();
2880 unsigned int odt_p = PARAM_UNDEFINED;
2881
2882 if (cs_num > 0 && cs_num <= MAX_CS_NUM)
2883 odt_p = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_p[cs_num - 1]);
2884
2885 if (odt_p == PARAM_UNDEFINED)
2886 printf("error: %s: unsupported odt_p parameter found\n", __func__);
2887
2888 return odt_p;
2889}
2890
2891unsigned int mv_ddr_misl_phy_odt_n_get(void)
2892{
2893 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2894 unsigned int cs_num = mv_ddr_cs_num_get();
2895 unsigned int odt_n = PARAM_UNDEFINED;
2896
2897 if (cs_num > 0 && cs_num <= MAX_CS_NUM)
2898 odt_n = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_n[cs_num - 1]);
2899
2900 if (odt_n == PARAM_UNDEFINED)
2901 printf("error: %s: unsupported odt_n parameter found\n", __func__);
2902
2903 return odt_n;
2904}
2905
