1#ifndef _AT91_I2C_H 2#define _AT91_I2C_H 3 4#include <linux/bitops.h> 5#define TWI_CR_START BIT(0) /* Send a Start Condition */ 6#define TWI_CR_MSEN BIT(2) /* Master Transfer Enable */ 7#define TWI_CR_STOP BIT(1) /* Send a Stop Condition */ 8#define TWI_CR_SVDIS BIT(5) /* Slave Transfer Disable */ 9#define TWI_CR_SWRST BIT(7) /* Software Reset */ 10#define TWI_CR_ACMEN BIT(16) /* Alternative Command Mode Enable */ 11#define TWI_CR_ACMDIS BIT(17) /* Alternative Command Mode Disable */ 12#define TWI_CR_LOCKCLR BIT(26) /* Lock Clear */ 13 14#define TWI_MMR_MREAD BIT(12) /* Master Read Direction */ 15#define TWI_MMR_IADRSZ_1 BIT(8) /* Internal Device Address Size */ 16 17#define TWI_SR_TXCOMP BIT(0) /* Transmission Complete */ 18#define TWI_SR_RXRDY BIT(1) /* Receive Holding Register Ready */ 19#define TWI_SR_TXRDY BIT(2) /* Transmit Holding Register Ready */ 20#define TWI_SR_OVRE BIT(6) /* Overrun Error */ 21#define TWI_SR_UNRE BIT(7) /* Underrun Error */ 22#define TWI_SR_NACK BIT(8) /* Not Acknowledged */ 23#define TWI_SR_LOCK BIT(23) /* TWI Lock due to Frame Errors */ 24 25#define TWI_ACR_DATAL(len) ((len) & 0xff) 26#define TWI_ACR_DIR_READ BIT(8) 27 28#define TWI_CWGR_HOLD_MAX 0x1f 29#define TWI_CWGR_HOLD(x) (((x) & TWI_CWGR_HOLD_MAX) << 24) 30 31struct at91_i2c_regs { 32 u32 cr; 33 u32 mmr; 34 u32 smr; 35 u32 iadr; 36 u32 cwgr; 37 u32 rev_0[3]; 38 u32 sr; 39 u32 ier; 40 u32 idr; 41 u32 imr; 42 u32 rhr; 43 u32 thr; 44 u32 smbtr; 45 u32 rev_1; 46 u32 acr; 47 u32 filtr; 48 u32 rev_2; 49 u32 swmr; 50 u32 fmr; 51 u32 flr; 52 u32 rev_3; 53 u32 fsr; 54 u32 fier; 55 u32 fidr; 56 u32 fimr; 57 u32 rev_4[29]; 58 u32 wpmr; 59 u32 wpsr; 60 u32 rev_5[6]; 61}; 62 63struct at91_i2c_pdata { 64 unsigned clk_max_div; 65 unsigned clk_offset; 66}; 67 68struct at91_i2c_bus { 69 struct at91_i2c_regs *regs; 70 u32 status; 71 ulong bus_clk_rate; 72 u32 clock_frequency; 73 u32 speed; 74 u32 cwgr_val; 75 const struct at91_i2c_pdata *pdata; 76}; 77 78#endif 79