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6#include <common.h>
7#include <dm.h>
8#include <hwspinlock.h>
9#include <log.h>
10#include <malloc.h>
11#include <asm/arch/gpio.h>
12#include <asm/gpio.h>
13#include <asm/io.h>
14#include <dm/device_compat.h>
15#include <dm/lists.h>
16#include <dm/pinctrl.h>
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/libfdt.h>
20
21#define MAX_PINS_ONE_IP 70
22#define MODE_BITS_MASK 3
23#define OSPEED_MASK 3
24#define PUPD_MASK 3
25#define OTYPE_MSK 1
26#define AFR_MASK 0xF
27
28struct stm32_pinctrl_priv {
29 struct hwspinlock hws;
30 int pinctrl_ngpios;
31 struct list_head gpio_dev;
32};
33
34struct stm32_gpio_bank {
35 struct udevice *gpio_dev;
36 struct list_head list;
37};
38
39#ifndef CONFIG_SPL_BUILD
40
41static char pin_name[PINNAME_SIZE];
42#define PINMUX_MODE_COUNT 5
43static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
44 "gpio input",
45 "gpio output",
46 "analog",
47 "unknown",
48 "alt function",
49};
50
51static const char * const pinmux_bias[] = {
52 [STM32_GPIO_PUPD_NO] = "",
53 [STM32_GPIO_PUPD_UP] = "pull-up",
54 [STM32_GPIO_PUPD_DOWN] = "pull-down",
55};
56
57static const char * const pinmux_input[] = {
58 [STM32_GPIO_OTYPE_PP] = "push-pull",
59 [STM32_GPIO_OTYPE_OD] = "open-drain",
60};
61
62static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
63{
64 struct stm32_gpio_priv *priv = dev_get_priv(dev);
65 struct stm32_gpio_regs *regs = priv->regs;
66 u32 af;
67 u32 alt_shift = (offset % 8) * 4;
68 u32 alt_index = offset / 8;
69
70 af = (readl(®s->afr[alt_index]) &
71 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
72
73 return af;
74}
75
76static int stm32_populate_gpio_dev_list(struct udevice *dev)
77{
78 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
79 struct udevice *gpio_dev;
80 struct udevice *child;
81 struct stm32_gpio_bank *gpio_bank;
82 int ret;
83
84
85
86
87
88
89
90 list_for_each_entry(child, &dev->child_head, sibling_node) {
91 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
92 &gpio_dev);
93 if (ret < 0)
94 continue;
95
96 gpio_bank = malloc(sizeof(*gpio_bank));
97 if (!gpio_bank) {
98 dev_err(dev, "Not enough memory\n");
99 return -ENOMEM;
100 }
101
102 gpio_bank->gpio_dev = gpio_dev;
103 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
104 }
105
106 return 0;
107}
108
109static int stm32_pinctrl_get_pins_count(struct udevice *dev)
110{
111 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
112 struct gpio_dev_priv *uc_priv;
113 struct stm32_gpio_bank *gpio_bank;
114
115
116
117
118
119 if (priv->pinctrl_ngpios)
120 return priv->pinctrl_ngpios;
121
122 if (list_empty(&priv->gpio_dev))
123 stm32_populate_gpio_dev_list(dev);
124
125
126
127
128 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
129 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
130
131 priv->pinctrl_ngpios += uc_priv->gpio_count;
132 }
133
134 return priv->pinctrl_ngpios;
135}
136
137static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
138 unsigned int selector,
139 unsigned int *idx)
140{
141 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
142 struct stm32_gpio_bank *gpio_bank;
143 struct gpio_dev_priv *uc_priv;
144 int pin_count = 0;
145
146 if (list_empty(&priv->gpio_dev))
147 stm32_populate_gpio_dev_list(dev);
148
149
150 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
151 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
152
153 if (selector < (pin_count + uc_priv->gpio_count)) {
154
155
156
157
158 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
159 selector - pin_count);
160 if (IS_ERR_VALUE(*idx))
161 return NULL;
162
163 return gpio_bank->gpio_dev;
164 }
165 pin_count += uc_priv->gpio_count;
166 }
167
168 return NULL;
169}
170
171static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
172 unsigned int selector)
173{
174 struct gpio_dev_priv *uc_priv;
175 struct udevice *gpio_dev;
176 unsigned int gpio_idx;
177
178
179 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
180 if (!gpio_dev) {
181 snprintf(pin_name, PINNAME_SIZE, "Error");
182 } else {
183 uc_priv = dev_get_uclass_priv(gpio_dev);
184
185 snprintf(pin_name, PINNAME_SIZE, "%s%d",
186 uc_priv->bank_name,
187 gpio_idx);
188 }
189
190 return pin_name;
191}
192
193static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
194 unsigned int selector,
195 char *buf,
196 int size)
197{
198 struct udevice *gpio_dev;
199 struct stm32_gpio_priv *priv;
200 const char *label;
201 int mode;
202 int af_num;
203 unsigned int gpio_idx;
204 u32 pupd, otype;
205
206
207 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
208
209 if (!gpio_dev)
210 return -ENODEV;
211
212 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
213 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
214 selector, gpio_idx, mode);
215 priv = dev_get_priv(gpio_dev);
216 pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
217
218
219 switch (mode) {
220 case GPIOF_UNKNOWN:
221
222 return -EINVAL;
223 case GPIOF_UNUSED:
224 snprintf(buf, size, "%s", pinmux_mode[mode]);
225 break;
226 case GPIOF_FUNC:
227 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
228 snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num,
229 pinmux_bias[pupd]);
230 break;
231 case GPIOF_OUTPUT:
232 snprintf(buf, size, "%s %s %s",
233 pinmux_mode[mode], pinmux_bias[pupd],
234 label ? label : "");
235 break;
236 case GPIOF_INPUT:
237 otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
238 snprintf(buf, size, "%s %s %s %s",
239 pinmux_mode[mode], pinmux_input[otype],
240 pinmux_bias[pupd], label ? label : "");
241 break;
242 }
243
244 return 0;
245}
246
247#endif
248
249static int stm32_pinctrl_probe(struct udevice *dev)
250{
251 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
252 int ret;
253
254 INIT_LIST_HEAD(&priv->gpio_dev);
255
256
257 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
258 if (ret)
259 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
260 __func__, ret);
261
262 return 0;
263}
264
265static int stm32_gpio_config(struct gpio_desc *desc,
266 const struct stm32_gpio_ctl *ctl)
267{
268 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
269 struct stm32_gpio_regs *regs = priv->regs;
270 struct stm32_pinctrl_priv *ctrl_priv;
271 int ret;
272 u32 index;
273
274 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
275 ctl->pupd > 2 || ctl->speed > 3)
276 return -EINVAL;
277
278 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
279 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
280 if (ret == -ETIME) {
281 dev_err(desc->dev, "HWSpinlock timeout\n");
282 return ret;
283 }
284
285 index = (desc->offset & 0x07) * 4;
286 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
287 ctl->af << index);
288
289 index = desc->offset * 2;
290 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
291 ctl->mode << index);
292 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
293 ctl->speed << index);
294 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
295
296 index = desc->offset;
297 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
298
299 hwspinlock_unlock(&ctrl_priv->hws);
300
301 return 0;
302}
303
304static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
305{
306 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
307 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
308 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
309 gpio_dsc->pin);
310
311 return 0;
312}
313
314static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
315 ofnode node)
316{
317 gpio_fn &= 0x00FF;
318 gpio_ctl->af = 0;
319
320 switch (gpio_fn) {
321 case 0:
322 gpio_ctl->mode = STM32_GPIO_MODE_IN;
323 break;
324 case 1 ... 16:
325 gpio_ctl->mode = STM32_GPIO_MODE_AF;
326 gpio_ctl->af = gpio_fn - 1;
327 break;
328 case 17:
329 gpio_ctl->mode = STM32_GPIO_MODE_AN;
330 break;
331 default:
332 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
333 break;
334 }
335
336 gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
337
338 if (ofnode_read_bool(node, "drive-open-drain"))
339 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
340 else
341 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
342
343 if (ofnode_read_bool(node, "bias-pull-up"))
344 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
345 else if (ofnode_read_bool(node, "bias-pull-down"))
346 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
347 else
348 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
349
350 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
351 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
352 gpio_ctl->pupd);
353
354 return 0;
355}
356
357static int stm32_pinctrl_config(ofnode node)
358{
359 u32 pin_mux[MAX_PINS_ONE_IP];
360 int rv, len;
361 ofnode subnode;
362
363
364
365
366
367 ofnode_for_each_subnode(subnode, node) {
368 struct stm32_gpio_dsc gpio_dsc;
369 struct stm32_gpio_ctl gpio_ctl;
370 int i;
371
372 rv = ofnode_read_size(subnode, "pinmux");
373 if (rv < 0)
374 return rv;
375 len = rv / sizeof(pin_mux[0]);
376 debug("%s: no of pinmux entries= %d\n", __func__, len);
377 if (len > MAX_PINS_ONE_IP)
378 return -EINVAL;
379 rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
380 if (rv < 0)
381 return rv;
382 for (i = 0; i < len; i++) {
383 struct gpio_desc desc;
384
385 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
386 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
387 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
388 rv = uclass_get_device_by_seq(UCLASS_GPIO,
389 gpio_dsc.port,
390 &desc.dev);
391 if (rv)
392 return rv;
393 desc.offset = gpio_dsc.pin;
394 rv = stm32_gpio_config(&desc, &gpio_ctl);
395 debug("%s: rv = %d\n\n", __func__, rv);
396 if (rv)
397 return rv;
398 }
399 }
400
401 return 0;
402}
403
404static int stm32_pinctrl_bind(struct udevice *dev)
405{
406 ofnode node;
407 const char *name;
408 int ret;
409
410 dev_for_each_subnode(node, dev) {
411 debug("%s: bind %s\n", __func__, ofnode_get_name(node));
412
413 ofnode_get_property(node, "gpio-controller", &ret);
414 if (ret < 0)
415 continue;
416
417 name = ofnode_get_name(node);
418 if (!name)
419 return -EINVAL;
420
421
422 ret = device_bind_driver_to_node(dev, "gpio_stm32",
423 name, node, NULL);
424 if (ret)
425 return ret;
426
427 debug("%s: bind %s\n", __func__, name);
428 }
429
430 return 0;
431}
432
433#if CONFIG_IS_ENABLED(PINCTRL_FULL)
434static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
435{
436 return stm32_pinctrl_config(dev_ofnode(config));
437}
438#else
439static int stm32_pinctrl_set_state_simple(struct udevice *dev,
440 struct udevice *periph)
441{
442 const fdt32_t *list;
443 uint32_t phandle;
444 ofnode config_node;
445 int size, i, ret;
446
447 list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
448 if (!list)
449 return -EINVAL;
450
451 debug("%s: periph->name = %s\n", __func__, periph->name);
452
453 size /= sizeof(*list);
454 for (i = 0; i < size; i++) {
455 phandle = fdt32_to_cpu(*list++);
456
457 config_node = ofnode_get_by_phandle(phandle);
458 if (!ofnode_valid(config_node)) {
459 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
460 return -EINVAL;
461 }
462
463 ret = stm32_pinctrl_config(config_node);
464 if (ret)
465 return ret;
466 }
467
468 return 0;
469}
470#endif
471
472static struct pinctrl_ops stm32_pinctrl_ops = {
473#if CONFIG_IS_ENABLED(PINCTRL_FULL)
474 .set_state = stm32_pinctrl_set_state,
475#else
476 .set_state_simple = stm32_pinctrl_set_state_simple,
477#endif
478#ifndef CONFIG_SPL_BUILD
479 .get_pin_name = stm32_pinctrl_get_pin_name,
480 .get_pins_count = stm32_pinctrl_get_pins_count,
481 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
482#endif
483};
484
485static const struct udevice_id stm32_pinctrl_ids[] = {
486 { .compatible = "st,stm32f429-pinctrl" },
487 { .compatible = "st,stm32f469-pinctrl" },
488 { .compatible = "st,stm32f746-pinctrl" },
489 { .compatible = "st,stm32f769-pinctrl" },
490 { .compatible = "st,stm32h743-pinctrl" },
491 { .compatible = "st,stm32mp157-pinctrl" },
492 { .compatible = "st,stm32mp157-z-pinctrl" },
493 { }
494};
495
496U_BOOT_DRIVER(pinctrl_stm32) = {
497 .name = "pinctrl_stm32",
498 .id = UCLASS_PINCTRL,
499 .of_match = stm32_pinctrl_ids,
500 .ops = &stm32_pinctrl_ops,
501 .bind = stm32_pinctrl_bind,
502 .probe = stm32_pinctrl_probe,
503 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
504};
505
