1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Freescale MCF5373 FireEngine board. 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M5373EVB_H 14#define _M5373EVB_H 15 16#include <linux/stringify.h> 17 18/* 19 * High Level Configuration Options 20 * (easy to change) 21 */ 22 23#define CONFIG_MCFUART 24#define CONFIG_SYS_UART_PORT (0) 25 26#undef CONFIG_WATCHDOG 27#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 28 29#define CONFIG_SYS_UNIFY_CACHE 30 31#ifdef CONFIG_MCFFEC 32# define CONFIG_MII_INIT 1 33# define CONFIG_SYS_DISCOVER_PHY 34# define CONFIG_SYS_RX_ETH_BUFFER 8 35# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 36/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 37# ifndef CONFIG_SYS_DISCOVER_PHY 38# define FECDUPLEX FULL 39# define FECSPEED _100BASET 40# else 41# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 42# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 43# endif 44# endif /* CONFIG_SYS_DISCOVER_PHY */ 45#endif 46 47#define CONFIG_MCFRTC 48#undef RTC_DEBUG 49 50/* Timer */ 51#define CONFIG_MCFTMR 52 53/* I2C */ 54#define CONFIG_SYS_I2C 55#define CONFIG_SYS_I2C_FSL 56#define CONFIG_SYS_FSL_I2C_SPEED 80000 57#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 58#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 59#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 60 61#define CONFIG_UDP_CHECKSUM 62 63#ifdef CONFIG_MCFFEC 64# define CONFIG_IPADDR 192.162.1.2 65# define CONFIG_NETMASK 255.255.255.0 66# define CONFIG_SERVERIP 192.162.1.1 67# define CONFIG_GATEWAYIP 192.162.1.1 68#endif /* FEC_ENET */ 69 70#define CONFIG_HOSTNAME "M5373EVB" 71#define CONFIG_EXTRA_ENV_SETTINGS \ 72 "netdev=eth0\0" \ 73 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 74 "u-boot=u-boot.bin\0" \ 75 "load=tftp ${loadaddr) ${u-boot}\0" \ 76 "upd=run load; run prog\0" \ 77 "prog=prot off 0 3ffff;" \ 78 "era 0 3ffff;" \ 79 "cp.b ${loadaddr} 0 ${filesize};" \ 80 "save\0" \ 81 "" 82 83#define CONFIG_PRAM 512 /* 512 KB */ 84 85#define CONFIG_SYS_LOAD_ADDR 0x40010000 86 87#define CONFIG_SYS_CLK 80000000 88#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 89 90#define CONFIG_SYS_MBAR 0xFC000000 91 92#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 93 94/* 95 * Low Level Configuration Settings 96 * (address mappings, register initial values, etc.) 97 * You should know what you are doing if you make changes here. 98 */ 99/*----------------------------------------------------------------------- 100 * Definitions for initial stack pointer and data area (in DPRAM) 101 */ 102#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 103#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 104#define CONFIG_SYS_INIT_RAM_CTRL 0x221 105#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 106#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 107 108/*----------------------------------------------------------------------- 109 * Start addresses for the final memory configuration 110 * (Set up by the startup code) 111 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 112 */ 113#define CONFIG_SYS_SDRAM_BASE 0x40000000 114#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 115#define CONFIG_SYS_SDRAM_CFG1 0x53722730 116#define CONFIG_SYS_SDRAM_CFG2 0x56670000 117#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 118#define CONFIG_SYS_SDRAM_EMOD 0x40010000 119#define CONFIG_SYS_SDRAM_MODE 0x018D0000 120 121#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 122#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 123 124#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 125#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 126 127/* 128 * For booting Linux, the board info and command line data 129 * have to be in the first 8 MB of memory, since this is 130 * the maximum mapped by the Linux kernel during initialization ?? 131 */ 132#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 133#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 134 135/*----------------------------------------------------------------------- 136 * FLASH organization 137 */ 138#ifdef CONFIG_SYS_FLASH_CFI 139# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 140# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 141# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 142# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 143#endif 144 145#ifdef CONFIG_NANDFLASH_SIZE 146# define CONFIG_SYS_MAX_NAND_DEVICE 1 147# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 148# define CONFIG_SYS_NAND_SIZE 1 149# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 150# define NAND_ALLOW_ERASE_ALL 1 151# define CONFIG_JFFS2_NAND 1 152# define CONFIG_JFFS2_DEV "nand0" 153# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 154# define CONFIG_JFFS2_PART_OFFSET 0x00000000 155#endif 156 157#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 158 159/* Configuration for environment 160 * Environment is embedded in u-boot in the second sector of the flash 161 */ 162 163#define LDS_BOARD_TEXT \ 164 . = DEFINED(env_offset) ? env_offset : .; \ 165 env/embedded.o(.text*); 166 167/*----------------------------------------------------------------------- 168 * Cache Configuration 169 */ 170#define CONFIG_SYS_CACHELINE_SIZE 16 171 172#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 173 CONFIG_SYS_INIT_RAM_SIZE - 8) 174#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 175 CONFIG_SYS_INIT_RAM_SIZE - 4) 176#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 177#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 178 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 179 CF_ACR_EN | CF_ACR_SM_ALL) 180#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 181 CF_CACR_DCM_P) 182 183/*----------------------------------------------------------------------- 184 * Chipselect bank definitions 185 */ 186/* 187 * CS0 - NOR Flash 1, 2, 4, or 8MB 188 * CS1 - CompactFlash and registers 189 * CS2 - NAND Flash 16, 32, or 64MB 190 * CS3 - Available 191 * CS4 - Available 192 * CS5 - Available 193 */ 194#define CONFIG_SYS_CS0_BASE 0 195#define CONFIG_SYS_CS0_MASK 0x007f0001 196#define CONFIG_SYS_CS0_CTRL 0x00001fa0 197 198#define CONFIG_SYS_CS1_BASE 0x10000000 199#define CONFIG_SYS_CS1_MASK 0x001f0001 200#define CONFIG_SYS_CS1_CTRL 0x002A3780 201 202#ifdef CONFIG_NANDFLASH_SIZE 203#define CONFIG_SYS_CS2_BASE 0x20000000 204#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 205#define CONFIG_SYS_CS2_CTRL 0x00001f60 206#endif 207 208#endif /* _M5373EVB_H */ 209