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38
39#ifndef __CONFIG_H
40#define __CONFIG_H
41
42#define CONFIG_MISC_INIT_F
43
44
45
46
47
48#ifdef CONFIG_TARGET_MPC8349ITX
49
50#define CONFIG_COMPACT_FLASH
51#define CONFIG_VSC7385_ENET
52#define CONFIG_SYS_USB_HOST
53#endif
54
55#include <linux/stringify.h>
56#define CONFIG_RTC_DS1337
57#define CONFIG_SYS_I2C
58
59
60
61
62
63
64#ifdef CONFIG_SYS_I2C
65#define CONFIG_SYS_I2C_FSL
66#define CONFIG_SYS_FSL_I2C_SPEED 400000
67#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
68#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
69#define CONFIG_SYS_FSL_I2C2_SPEED 400000
70#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
71#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
72
73#define CONFIG_SYS_SPD_BUS_NUM 1
74#define CONFIG_SYS_RTC_BUS_NUM 1
75
76#define CONFIG_SYS_I2C_8574_ADDR1 0x20
77#define CONFIG_SYS_I2C_8574_ADDR2 0x21
78#define CONFIG_SYS_I2C_8574A_ADDR1 0x38
79#define CONFIG_SYS_I2C_8574A_ADDR2 0x39
80#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
81#define CONFIG_SYS_I2C_RTC_ADDR 0x68
82#define SPD_EEPROM_ADDRESS 0x51
83
84
85#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
86 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
87 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
88 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
89
90
91#define I2C_8574_REVISION 0x03
92#define I2C_8574_CF 0x08
93#define I2C_8574_MPCICLKRN 0x10
94#define I2C_8574_PCI66 0x20
95#define I2C_8574_FLASHSIDE 0x40
96
97#endif
98
99
100#ifdef CONFIG_COMPACT_FLASH
101
102#define CONFIG_SYS_IDE_MAXBUS 1
103#define CONFIG_SYS_IDE_MAXDEVICE 1
104
105#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
106#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
107#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
108#define CONFIG_SYS_ATA_REG_OFFSET 0
109#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
110#define CONFIG_SYS_ATA_STRIDE 2
111
112
113#define ATA_RESET_TIME 1
114
115#endif
116
117
118
119
120#ifdef CONFIG_SATA_SIL3114
121
122#define CONFIG_SYS_SATA_MAX_DEVICE 4
123#define CONFIG_LBA48
124
125#endif
126
127#ifdef CONFIG_SYS_USB_HOST
128
129
130
131#define CONFIG_USB_EHCI_FSL
132
133
134
135#if 1
136#define CONFIG_HAS_FSL_MPH_USB
137#else
138#define CONFIG_HAS_FSL_DR_USB
139#endif
140
141#endif
142
143
144
145
146#define CONFIG_SYS_SDRAM_BASE 0x00000000
147#define CONFIG_SYS_83XX_DDR_USES_CS0
148
149#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
150 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
151
152#define CONFIG_VERY_BIG_RAM
153#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
154
155#ifdef CONFIG_SYS_I2C
156#define CONFIG_SPD_EEPROM
157#endif
158
159
160#ifndef CONFIG_SPD_EEPROM
161 #define CONFIG_SYS_DDR_SIZE 256
162 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
163 | CSCONFIG_ROW_BIT_13 \
164 | CSCONFIG_COL_BIT_10)
165
166 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
167 #define CONFIG_SYS_DDR_TIMING_2 0x00000800
168#endif
169
170
171
172
173
174#define CONFIG_SYS_FLASH_BASE 0xFE000000
175#define CONFIG_SYS_FLASH_EMPTY_INFO
176
177#define CONFIG_SYS_MAX_FLASH_SECT 135
178#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
179#define CONFIG_SYS_FLASH_WRITE_TOUT 500
180#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
181
182
183
184#define CONFIG_SYS_FLASH_QUIET_TEST
185#define CONFIG_SYS_MAX_FLASH_BANKS 2
186#define CONFIG_SYS_FLASH_BANKS_LIST \
187 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
188#define CONFIG_SYS_FLASH_SIZE 16
189
190
191
192#ifdef CONFIG_VSC7385_ENET
193
194#define CONFIG_TSEC2
195
196
197#define CONFIG_VSC7385_IMAGE 0xFEFFE000
198#define CONFIG_VSC7385_IMAGE_SIZE 8192
199
200#endif
201
202
203
204
205
206
207
208
209#define CONFIG_SYS_VSC7385_BASE 0xF8000000
210
211#define CONFIG_SYS_LED_BASE 0xF9000000
212
213
214
215
216#ifdef CONFIG_COMPACT_FLASH
217
218#define CONFIG_SYS_CF_BASE 0xF0000000
219
220
221#endif
222
223
224
225
226#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
227
228#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
229#define CONFIG_SYS_RAMBOOT
230#else
231#undef CONFIG_SYS_RAMBOOT
232#endif
233
234#define CONFIG_SYS_INIT_RAM_LOCK
235#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
236#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
237
238#define CONFIG_SYS_GBL_DATA_OFFSET \
239 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
240#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
241
242
243#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
244#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
245
246
247
248
249#define CONFIG_SYS_NS16550_SERIAL
250#define CONFIG_SYS_NS16550_REG_SIZE 1
251#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
252
253#define CONFIG_SYS_BAUDRATE_TABLE \
254 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
255
256#define CONSOLE ttyS0
257
258#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
259#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
260
261
262
263
264#ifdef CONFIG_PCI
265#define CONFIG_PCI_INDIRECT_BRIDGE
266
267#define CONFIG_MPC83XX_PCI2
268
269
270
271
272
273#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
274#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
275#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
276#define CONFIG_SYS_PCI1_MMIO_BASE \
277 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
278#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
279#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
280#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
281#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
282#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
283
284#ifdef CONFIG_MPC83XX_PCI2
285#define CONFIG_SYS_PCI2_MEM_BASE \
286 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
287#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
288#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
289#define CONFIG_SYS_PCI2_MMIO_BASE \
290 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
291#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
292#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
293#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
294#define CONFIG_SYS_PCI2_IO_PHYS \
295 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
296#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000
297#endif
298
299#ifndef CONFIG_PCI_PNP
300 #define PCI_ENET0_IOADDR 0x00000000
301 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
302 #define PCI_IDSEL_NUMBER 0x0f
303#endif
304
305#define CONFIG_PCI_SCAN_SHOW
306
307#endif
308
309
310
311#ifdef CONFIG_TSEC_ENET
312#define CONFIG_TSEC1
313
314#ifdef CONFIG_TSEC1
315#define CONFIG_HAS_ETH0
316#define CONFIG_TSEC1_NAME "TSEC0"
317#define CONFIG_SYS_TSEC1_OFFSET 0x24000
318#define TSEC1_PHY_ADDR 0x1c
319#define TSEC1_PHYIDX 0
320#define TSEC1_FLAGS TSEC_GIGABIT
321#endif
322
323#ifdef CONFIG_TSEC2
324#define CONFIG_HAS_ETH1
325#define CONFIG_TSEC2_NAME "TSEC1"
326#define CONFIG_SYS_TSEC2_OFFSET 0x25000
327
328#define TSEC2_PHY_ADDR 4
329#define TSEC2_PHYIDX 0
330#define TSEC2_FLAGS TSEC_GIGABIT
331#endif
332
333#define CONFIG_ETHPRIME "Freescale TSEC"
334
335#endif
336
337
338
339
340
341#define CONFIG_LOADS_ECHO
342#define CONFIG_SYS_LOADS_BAUD_CHANGE
343
344
345
346
347#define CONFIG_BOOTP_BOOTFILESIZE
348
349
350#undef CONFIG_WATCHDOG
351
352
353
354
355
356#define CONFIG_SYS_LOAD_ADDR 0x2000000
357#define CONFIG_LOADADDR 800000
358
359
360
361
362
363
364
365#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
366#define CONFIG_SYS_BOOTM_LEN (64 << 20)
367
368
369
370
371#define CONFIG_SYS_SCCR_TSEC1CM 1
372#define CONFIG_SYS_SCCR_TSEC2CM 1
373#define CONFIG_SYS_SCCR_USBMPHCM 3
374#define CONFIG_SYS_SCCR_USBDRCM 0
375
376
377
378
379
380#define CONFIG_SYS_SICRH SICRH_TSOBI1
381
382#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
383
384#if defined(CONFIG_CMD_KGDB)
385#define CONFIG_KGDB_BAUDRATE 230400
386#endif
387
388
389
390
391
392#define CONFIG_NETDEV "eth0"
393
394
395#define CONFIG_ROOTPATH "/nfsroot/rootfs"
396#define CONFIG_BOOTFILE "uImage"
397
398#define CONFIG_UBOOTPATH "u-boot.bin"
399
400#ifdef CONFIG_TARGET_MPC8349ITX
401#define CONFIG_FDTFILE "mpc8349emitx.dtb"
402#else
403#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
404#endif
405
406
407#define CONFIG_EXTRA_ENV_SETTINGS \
408 "console=" __stringify(CONSOLE) "\0" \
409 "netdev=" CONFIG_NETDEV "\0" \
410 "uboot=" CONFIG_UBOOTPATH "\0" \
411 "tftpflash=tftpboot $loadaddr $uboot; " \
412 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
413 " +$filesize; " \
414 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
415 " +$filesize; " \
416 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
417 " $filesize; " \
418 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
419 " +$filesize; " \
420 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
421 " $filesize\0" \
422 "fdtaddr=780000\0" \
423 "fdtfile=" CONFIG_FDTFILE "\0"
424
425#define CONFIG_NFSBOOTCOMMAND \
426 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
427 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
428 " console=$console,$baudrate $othbootargs; " \
429 "tftp $loadaddr $bootfile;" \
430 "tftp $fdtaddr $fdtfile;" \
431 "bootm $loadaddr - $fdtaddr"
432
433#define CONFIG_RAMBOOTCOMMAND \
434 "setenv bootargs root=/dev/ram rw" \
435 " console=$console,$baudrate $othbootargs; " \
436 "tftp $ramdiskaddr $ramdiskfile;" \
437 "tftp $loadaddr $bootfile;" \
438 "tftp $fdtaddr $fdtfile;" \
439 "bootm $loadaddr $ramdiskaddr $fdtaddr"
440
441#endif
442