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17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20
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22
23
24
25#ifndef CONFIG_HAS_FEC
26#define CONFIG_HAS_FEC 1
27#endif
28
29#define CONFIG_PCI_INDIRECT_BRIDGE
30#define CONFIG_SYS_PCI_64BIT 1
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48
49
50#ifndef CONFIG_SYS_CLK_FREQ
51#define CONFIG_SYS_CLK_FREQ 33000000
52#endif
53
54
55
56
57#define CONFIG_L2_CACHE
58#define CONFIG_BTB
59
60#define CONFIG_SYS_CCSRBAR 0xe0000000
61#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
62
63
64#define CONFIG_SPD_EEPROM
65#define CONFIG_DDR_SPD
66
67#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
68
69#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
70#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
71
72#define CONFIG_DIMM_SLOTS_PER_CTLR 1
73#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
74
75
76#define SPD_EEPROM_ADDRESS 0x51
77
78
79#define CONFIG_SYS_SDRAM_SIZE 128
80#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
81#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
82#define CONFIG_SYS_DDR_TIMING_1 0x37344321
83#define CONFIG_SYS_DDR_TIMING_2 0x00000800
84#define CONFIG_SYS_DDR_CONTROL 0xc2000000
85#define CONFIG_SYS_DDR_MODE 0x00000062
86#define CONFIG_SYS_DDR_INTERVAL 0x05200100
87
88
89
90
91#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
92#define CONFIG_SYS_LBC_SDRAM_SIZE 64
93
94#define CONFIG_SYS_FLASH_BASE 0xff000000
95#define CONFIG_SYS_BR0_PRELIM 0xff001801
96
97#define CONFIG_SYS_OR0_PRELIM 0xff006ff7
98#define CONFIG_SYS_MAX_FLASH_BANKS 1
99#define CONFIG_SYS_MAX_FLASH_SECT 64
100#undef CONFIG_SYS_FLASH_CHECKSUM
101#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
102#define CONFIG_SYS_FLASH_WRITE_TOUT 500
103
104#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
105
106#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
107#define CONFIG_SYS_RAMBOOT
108#else
109#undef CONFIG_SYS_RAMBOOT
110#endif
111
112#define CONFIG_SYS_FLASH_EMPTY_INFO
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135
136#define CONFIG_SYS_BR2_PRELIM 0xf0001861
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151
152#define CONFIG_SYS_OR2_PRELIM 0xfc006901
153
154#define CONFIG_SYS_LBC_LCRR 0x00030004
155#define CONFIG_SYS_LBC_LBCR 0x00000000
156#define CONFIG_SYS_LBC_LSRT 0x20000000
157#define CONFIG_SYS_LBC_MRTPR 0x20000000
158
159#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
160 | LSDMR_RFCR5 \
161 | LSDMR_PRETOACT3 \
162 | LSDMR_ACTTORW3 \
163 | LSDMR_BL8 \
164 | LSDMR_WRC2 \
165 | LSDMR_CL3 \
166 | LSDMR_RFEN \
167 )
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170
171
172#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
173#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
174#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
175#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
176#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
177
178
179
180
181#define CONFIG_SYS_BR4_PRELIM 0xf8000801
182#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
183#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
184
185#define CONFIG_SYS_INIT_RAM_LOCK 1
186#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
187#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
188
189#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
190#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
191
192#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
193#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
194
195
196#define CONFIG_SYS_NS16550_SERIAL
197#define CONFIG_SYS_NS16550_REG_SIZE 1
198#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
199
200#define CONFIG_SYS_BAUDRATE_TABLE \
201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
202
203#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
204#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
205
206
207
208
209#define CONFIG_SYS_I2C
210#define CONFIG_SYS_I2C_FSL
211#define CONFIG_SYS_FSL_I2C_SPEED 400000
212#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
213#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
214#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
215
216
217#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000
218#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000
219#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
220#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000
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225
226#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
227#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
228#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
229#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
230#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
231#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
232#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
233#define CONFIG_SYS_PCI1_IO_SIZE 0x100000
234
235#if defined(CONFIG_PCI)
236
237#if !defined(CONFIG_PCI_PNP)
238 #define PCI_ENET0_IOADDR 0xe0000000
239 #define PCI_ENET0_MEMADDR 0xe0000000
240 #define PCI_IDSEL_NUMBER 0x0c
241#endif
242
243#undef CONFIG_PCI_SCAN_SHOW
244#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
245
246#endif
247
248#if defined(CONFIG_TSEC_ENET)
249
250#define CONFIG_TSEC1 1
251#define CONFIG_TSEC1_NAME "TSEC0"
252#define CONFIG_TSEC2 1
253#define CONFIG_TSEC2_NAME "TSEC1"
254#define TSEC1_PHY_ADDR 0
255#define TSEC2_PHY_ADDR 1
256#define TSEC1_PHYIDX 0
257#define TSEC2_PHYIDX 0
258#define TSEC1_FLAGS TSEC_GIGABIT
259#define TSEC2_FLAGS TSEC_GIGABIT
260
261#if CONFIG_HAS_FEC
262#define CONFIG_MPC85XX_FEC 1
263#define CONFIG_MPC85XX_FEC_NAME "FEC"
264#define FEC_PHY_ADDR 3
265#define FEC_PHYIDX 0
266#define FEC_FLAGS 0
267#endif
268
269
270#define CONFIG_ETHPRIME "TSEC0"
271
272#endif
273
274
275
276
277
278#define CONFIG_LOADS_ECHO 1
279#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
280
281
282
283
284#define CONFIG_BOOTP_BOOTFILESIZE
285
286#undef CONFIG_WATCHDOG
287
288
289
290
291#define CONFIG_SYS_LOAD_ADDR 0x2000000
292
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296
297
298#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
299#define CONFIG_SYS_BOOTM_LEN (64 << 20)
300
301#if defined(CONFIG_CMD_KGDB)
302#define CONFIG_KGDB_BAUDRATE 230400
303#endif
304
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309
310#if defined(CONFIG_TSEC_ENET)
311#define CONFIG_HAS_ETH0
312#define CONFIG_HAS_ETH1
313#define CONFIG_HAS_ETH2
314#endif
315
316#define CONFIG_IPADDR 192.168.1.253
317
318#define CONFIG_HOSTNAME "unknown"
319#define CONFIG_ROOTPATH "/nfsroot"
320#define CONFIG_BOOTFILE "your.uImage"
321
322#define CONFIG_SERVERIP 192.168.1.1
323#define CONFIG_GATEWAYIP 192.168.1.1
324#define CONFIG_NETMASK 255.255.255.0
325
326#define CONFIG_LOADADDR 200000
327
328#define CONFIG_EXTRA_ENV_SETTINGS \
329 "netdev=eth0\0" \
330 "consoledev=ttyS0\0" \
331 "ramdiskaddr=1000000\0" \
332 "ramdiskfile=your.ramdisk.u-boot\0" \
333 "fdtaddr=400000\0" \
334 "fdtfile=your.fdt.dtb\0"
335
336#define CONFIG_NFSBOOTCOMMAND \
337 "setenv bootargs root=/dev/nfs rw " \
338 "nfsroot=$serverip:$rootpath " \
339 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
340 "console=$consoledev,$baudrate $othbootargs;" \
341 "tftp $loadaddr $bootfile;" \
342 "tftp $fdtaddr $fdtfile;" \
343 "bootm $loadaddr - $fdtaddr"
344
345#define CONFIG_RAMBOOTCOMMAND \
346 "setenv bootargs root=/dev/ram rw " \
347 "console=$consoledev,$baudrate $othbootargs;" \
348 "tftp $ramdiskaddr $ramdiskfile;" \
349 "tftp $loadaddr $bootfile;" \
350 "tftp $fdtaddr $fdtfile;" \
351 "bootm $loadaddr $ramdiskaddr $fdtaddr"
352
353#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
354
355#endif
356