1
2
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4
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
9#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
10
11#define CONFIG_SYS_FSL_CLK
12
13#define CONFIG_DEEP_SLEEP
14
15
16#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
17
18#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
19#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
20
21
22#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
23
24#define CONFIG_SYS_CLK_FREQ 100000000
25#define CONFIG_DDR_CLK_FREQ 100000000
26
27#define DDR_SDRAM_CFG 0x470c0008
28#define DDR_CS0_BNDS 0x008000bf
29#define DDR_CS0_CONFIG 0x80014302
30#define DDR_TIMING_CFG_0 0x50550004
31#define DDR_TIMING_CFG_1 0xbcb38c56
32#define DDR_TIMING_CFG_2 0x0040d120
33#define DDR_TIMING_CFG_3 0x010e1000
34#define DDR_TIMING_CFG_4 0x00000001
35#define DDR_TIMING_CFG_5 0x03401400
36#define DDR_SDRAM_CFG_2 0x00401010
37#define DDR_SDRAM_MODE 0x00061c60
38#define DDR_SDRAM_MODE_2 0x00180000
39#define DDR_SDRAM_INTERVAL 0x18600618
40#define DDR_DDR_WRLVL_CNTL 0x8655f605
41#define DDR_DDR_WRLVL_CNTL_2 0x05060607
42#define DDR_DDR_WRLVL_CNTL_3 0x05050505
43#define DDR_DDR_CDR1 0x80040000
44#define DDR_DDR_CDR2 0x00000001
45#define DDR_SDRAM_CLK_CNTL 0x02000000
46#define DDR_DDR_ZQ_CNTL 0x89080600
47#define DDR_CS0_CONFIG_2 0
48#define DDR_SDRAM_CFG_MEM_EN 0x80000000
49#define SDRAM_CFG2_D_INIT 0x00000010
50#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
51#define SDRAM_CFG2_FRC_SR 0x80000000
52#define SDRAM_CFG_BI 0x00000001
53
54#ifdef CONFIG_RAMBOOT_PBL
55#define CONFIG_SYS_FSL_PBL_PBI \
56 "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
57#endif
58
59#ifdef CONFIG_SD_BOOT
60#define CONFIG_SYS_FSL_PBL_RCW \
61 "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
62
63#ifdef CONFIG_NXP_ESBC
64#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
65#endif
66
67#define CONFIG_SPL_MAX_SIZE 0x1a000
68#define CONFIG_SPL_STACK 0x1001d000
69#define CONFIG_SPL_PAD_TO 0x1c000
70
71#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
72 CONFIG_SYS_MONITOR_LEN)
73#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
74#define CONFIG_SPL_BSS_START_ADDR 0x80100000
75#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
76
77#ifdef CONFIG_U_BOOT_HDR_SIZE
78
79
80
81
82
83
84#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
85#else
86#define CONFIG_SYS_MONITOR_LEN 0x100000
87#endif
88#endif
89
90#define CONFIG_NR_DRAM_BANKS 1
91#define PHYS_SDRAM 0x80000000
92#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
93
94#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
95#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
96
97#define CONFIG_CHIP_SELECTS_PER_CTRL 4
98
99
100#define CONFIG_SYS_NS16550_SERIAL
101#ifndef CONFIG_DM_SERIAL
102#define CONFIG_SYS_NS16550_REG_SIZE 1
103#endif
104#define CONFIG_SYS_NS16550_CLK get_serial_clock()
105
106
107#ifndef CONFIG_DM_I2C
108#define CONFIG_SYS_I2C
109#else
110#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
111#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
112#endif
113#define CONFIG_SYS_I2C_MXC
114#define CONFIG_SYS_I2C_MXC_I2C1
115#define CONFIG_SYS_I2C_MXC_I2C2
116#define CONFIG_SYS_I2C_MXC_I2C3
117
118
119#define CONFIG_ID_EEPROM
120#define CONFIG_SYS_I2C_EEPROM_NXID
121#define CONFIG_SYS_EEPROM_BUS_NUM 0
122#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
123#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
124
125
126#define FSL_QSPI_FLASH_SIZE (1 << 24)
127#define FSL_QSPI_FLASH_NUM 2
128
129
130#define CONFIG_PCIE1
131#define CONFIG_PCIE2
132#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
133#ifdef CONFIG_PCI
134#define CONFIG_PCI_SCAN_SHOW
135#endif
136
137#define CONFIG_LAYERSCAPE_NS_ACCESS
138#define COUNTER_FREQUENCY 12500000
139
140#define CONFIG_HWCONFIG
141#define HWCONFIG_BUFFER_SIZE 256
142
143#define CONFIG_FSL_DEVICE_DISABLE
144
145#define BOOT_TARGET_DEVICES(func) \
146 func(MMC, mmc, 0) \
147 func(USB, usb, 0) \
148 func(DHCP, dhcp, na)
149#include <config_distro_bootcmd.h>
150
151#define CONFIG_EXTRA_ENV_SETTINGS \
152 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
153 "initrd_high=0xffffffff\0" \
154 "fdt_addr=0x64f00000\0" \
155 "kernel_addr=0x61000000\0" \
156 "kernelheader_addr=0x60800000\0" \
157 "scriptaddr=0x80000000\0" \
158 "scripthdraddr=0x80080000\0" \
159 "fdtheader_addr_r=0x80100000\0" \
160 "kernelheader_addr_r=0x80200000\0" \
161 "kernel_addr_r=0x80008000\0" \
162 "kernelheader_size=0x40000\0" \
163 "fdt_addr_r=0x8f000000\0" \
164 "ramdisk_addr_r=0xa0000000\0" \
165 "load_addr=0x80008000\0" \
166 "kernel_size=0x2800000\0" \
167 "kernel_addr_sd=0x8000\0" \
168 "kernel_size_sd=0x14000\0" \
169 "kernelhdr_addr_sd=0x4000\0" \
170 "kernelhdr_size_sd=0x10\0" \
171 BOOTENV \
172 "boot_scripts=ls1021atsn_boot.scr\0" \
173 "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
174 "scan_dev_for_boot_part=" \
175 "part list ${devtype} ${devnum} devplist; " \
176 "env exists devplist || setenv devplist 1; " \
177 "for distro_bootpart in ${devplist}; do " \
178 "if fstype ${devtype} " \
179 "${devnum}:${distro_bootpart} " \
180 "bootfstype; then " \
181 "run scan_dev_for_boot; " \
182 "fi; " \
183 "done\0" \
184 "scan_dev_for_boot=" \
185 "echo Scanning ${devtype} " \
186 "${devnum}:${distro_bootpart}...; " \
187 "for prefix in ${boot_prefixes}; do " \
188 "run scan_dev_for_scripts; " \
189 "run scan_dev_for_extlinux; " \
190 "done;" \
191 "\0" \
192 "boot_a_script=" \
193 "load ${devtype} ${devnum}:${distro_bootpart} " \
194 "${scriptaddr} ${prefix}${script}; " \
195 "env exists secureboot && load ${devtype} " \
196 "${devnum}:${distro_bootpart} " \
197 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
198 "&& esbc_validate ${scripthdraddr};" \
199 "source ${scriptaddr}\0" \
200 "qspi_bootcmd=echo Trying load from qspi..;" \
201 "sf probe && sf read $load_addr " \
202 "$kernel_addr $kernel_size; env exists secureboot " \
203 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
204 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
205 "bootm $load_addr#$board\0" \
206 "sd_bootcmd=echo Trying load from SD ..;" \
207 "mmcinfo && mmc read $load_addr " \
208 "$kernel_addr_sd $kernel_size_sd && " \
209 "env exists secureboot && mmc read $kernelheader_addr_r " \
210 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
211 " && esbc_validate ${kernelheader_addr_r};" \
212 "bootm $load_addr#$board\0"
213
214
215#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
216
217#define CONFIG_SYS_CBSIZE 256
218#define CONFIG_SYS_PBSIZE \
219 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
220#define CONFIG_SYS_MAXARGS 16
221#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
222
223#define CONFIG_SYS_LOAD_ADDR 0x82000000
224
225#define CONFIG_LS102XA_STREAM_ID
226
227#define CONFIG_SYS_INIT_SP_OFFSET \
228 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
229#define CONFIG_SYS_INIT_SP_ADDR \
230 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
231
232#ifdef CONFIG_SPL_BUILD
233#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
234#else
235#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
236#endif
237
238
239
240#define CONFIG_SYS_BOOTM_LEN 0x8000000
241
242#endif
243
