LXR uboot/include/configs/socfpga_arria5

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2017-2020 Hitachi Power Grids
   4 *
   5 */
   6#ifndef __CONFIG_SOCFPGA_SECU1_H__
   7#define __CONFIG_SOCFPGA_SECU1_H__
   8
   9#include <asm/arch/base_addr_ac5.h>
  10#include <linux/stringify.h>
  11
  12/* Call misc_init_r */
  13#define CONFIG_MISC_INIT_R
  14
  15#define CONFIG_HUSH_INIT_VAR
  16/* Eternal oscillator */
  17#define CONFIG_SYS_TIMER_RATE   40000000
  18
  19/* Memory configurations */
  20#define PHYS_SDRAM_1_SIZE       0x20000000      /* 512MiB on SECU1 */
  21
  22/*
  23 * We use bootcounter in i2c nvram of the RTC (0x68)
  24 * The offset fopr the bootcounter is 0x9e, which are
  25 * the last two bytes of the 128 bytes large NVRAM in the
  26 * RTC which begin at address 0x20
  27 */
  28#define CONFIG_SYS_I2C_RTC_ADDR         0x68
  29
  30/* Booting Linux */
  31#define CONFIG_BOOTFILE         "zImage"
  32
  33#define CONFIG_BOOTCOMMAND      \
  34        "setenv bootcmd '"      \
  35                "bridge enable; "       \
  36                "if test ${bootnum} = \"b\"; " \
  37                      "then run _fpga_loadsafe; " \
  38                "else if test ${bootcount} -eq 4; then echo \"Switching copy...\"; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; " \
  39                      "run _fpga_loaduser; " \
  40                "fi;" \
  41                "echo \"Booting bank $bootnum\" && run userload && run userboot;" \
  42        "' && " \
  43        "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \
  44        "saveenv && saveenv && boot;"
  45
  46#define CONFIG_CMDLINE_TAG
  47#define CONFIG_SYS_BOOTM_LEN            (64 << 20)
  48
  49/* Environment settings */
  50
  51/*
  52 * Autoboot
  53 *
  54 * After 45s of inactivity in the prompt, the board will reset.
  55 * Set 'bootretry' in the environment to -1 to disable this behavior
  56 */
  57#define CONFIG_BOOT_RETRY_TIME 45
  58#define CONFIG_RESET_TO_RETRY
  59
  60#define CONFIG_LOADADDR         0x01000000
  61#define CONFIG_SYS_LOAD_ADDR   CONFIG_KM_KERNEL_ADDR
  62
  63/*
  64 * FPGA Remote Update related environment
  65 *
  66 * Note that since those commands access the FPGA, the HPS-to-FPGA
  67 * bridges MUST have been previously enabled (for example
  68 * with 'bridge enable').
  69 */
  70#define FPGA_RMTU_ENV \
  71        "rmtu_page=0xFF29000C\0" \
  72        "rmtu_reconfig=0xFF290018\0" \
  73        "fpga_safebase=0x0\0" \
  74        "fpga_userbase=0x2000000\0" \
  75        "_fpga_loaduser=echo Loading FPGA USER image..." \
  76                " && mw ${rmtu_page} ${fpga_userbase} && mw ${rmtu_reconfig} 1\0" \
  77        "_fpga_loadsafe=echo Loading FPGA SAFE image..." \
  78                " && mw ${rmtu_page} ${fpga_safebase} && mw ${rmtu_reconfig} 1\0" \
  79
  80#define CONFIG_KM_NEW_ENV \
  81        "newenv=" \
  82                "nand erase 0x100000 0x40000\0"
  83
  84#define CONFIG_KM_DEF_ENV_BOOTTARGETS \
  85        "release=" \
  86                "run newenv; reset\0" \
  87        "develop=" \
  88                "tftp 0x200000 scripts/develop-secu.txt && env import -t 0x200000 ${filesize} && saveenv && reset\0"
  89
  90#define CONFIG_EXTRA_ENV_SETTINGS \
  91        FPGA_RMTU_ENV \
  92        CONFIG_KM_DEF_ENV_BOOTTARGETS \
  93        CONFIG_KM_NEW_ENV \
  94        "socfpga_legacy_reset_compat=1\0"       \
  95        "altbootcmd=run bootcmd;\0"     \
  96        "bootlimit=6\0" \
  97        "bootnum=1\0" \
  98        "bootretry=" __stringify(CONFIG_BOOT_RETRY_TIME) "\0" \
  99        "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
 100        "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \
 101        "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \
 102        "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
 103        "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
 104        "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \
 105        "userload=ubi part nand.ubi &&" \
 106                "ubi check rootfs$bootnum &&" \
 107                "ubi read $fdt_addr dtb$bootnum &&" \
 108                "ubi read $loadaddr kernel$bootnum\0" \
 109        "userboot=setenv bootargs " CONFIG_BOOTARGS \
 110                " ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid"   \
 111                " ro rootfstype=squashfs init=sbin/preinit;" \
 112                "bootz ${loadaddr} - ${fdt_addr}\0" \
 113        "verify=y\0"
 114
 115/* The rest of the configuration is shared */
 116#include <configs/socfpga_common.h>
 117
 118#ifdef CONFIG_SPL_NAND_SUPPORT
 119#undef CONFIG_SYS_NAND_U_BOOT_OFFS
 120#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 121#endif
 122
 123#undef CONFIG_WATCHDOG_TIMEOUT_MSECS
 124#define CONFIG_WATCHDOG_TIMEOUT_MSECS   60000
 125
 126#endif  /* __CONFIG_SOCFPGA_SECU1_H__ */
 127