1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2019 Renesas Electronics Corp. 4 */ 5#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ 6#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ 7 8#include <dt-bindings/clock/renesas-cpg-mssr.h> 9 10/* r8a774a1 CPG Core Clocks */ 11#define R8A774A1_CLK_Z 0 12#define R8A774A1_CLK_Z2 1 13#define R8A774A1_CLK_ZG 2 14#define R8A774A1_CLK_ZTR 3 15#define R8A774A1_CLK_ZTRD2 4 16#define R8A774A1_CLK_ZT 5 17#define R8A774A1_CLK_ZX 6 18#define R8A774A1_CLK_S0D1 7 19#define R8A774A1_CLK_S0D2 8 20#define R8A774A1_CLK_S0D3 9 21#define R8A774A1_CLK_S0D4 10 22#define R8A774A1_CLK_S0D6 11 23#define R8A774A1_CLK_S0D8 12 24#define R8A774A1_CLK_S0D12 13 25#define R8A774A1_CLK_S1D2 14 26#define R8A774A1_CLK_S1D4 15 27#define R8A774A1_CLK_S2D1 16 28#define R8A774A1_CLK_S2D2 17 29#define R8A774A1_CLK_S2D4 18 30#define R8A774A1_CLK_S3D1 19 31#define R8A774A1_CLK_S3D2 20 32#define R8A774A1_CLK_S3D4 21 33#define R8A774A1_CLK_LB 22 34#define R8A774A1_CLK_CL 23 35#define R8A774A1_CLK_ZB3 24 36#define R8A774A1_CLK_ZB3D2 25 37#define R8A774A1_CLK_ZB3D4 26 38#define R8A774A1_CLK_CR 27 39#define R8A774A1_CLK_CRD2 28 40#define R8A774A1_CLK_SD0H 29 41#define R8A774A1_CLK_SD0 30 42#define R8A774A1_CLK_SD1H 31 43#define R8A774A1_CLK_SD1 32 44#define R8A774A1_CLK_SD2H 33 45#define R8A774A1_CLK_SD2 34 46#define R8A774A1_CLK_SD3H 35 47#define R8A774A1_CLK_SD3 36 48#define R8A774A1_CLK_RPC 37 49#define R8A774A1_CLK_RPCD2 38 50#define R8A774A1_CLK_MSO 39 51#define R8A774A1_CLK_HDMI 40 52#define R8A774A1_CLK_CSI0 41 53#define R8A774A1_CLK_CP 42 54#define R8A774A1_CLK_CPEX 43 55#define R8A774A1_CLK_R 44 56#define R8A774A1_CLK_OSC 45 57#define R8A774A1_CLK_CANFD 46 58 59#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ 60