1/* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * Copyright (C) 2015 Renesas Electronics Corp. 4 */ 5 6#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ 7#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ 8 9#include <dt-bindings/clock/renesas-cpg-mssr.h> 10 11/* r8a7790 CPG Core Clocks */ 12#define R8A7790_CLK_Z 0 13#define R8A7790_CLK_Z2 1 14#define R8A7790_CLK_ZG 2 15#define R8A7790_CLK_ZTR 3 16#define R8A7790_CLK_ZTRD2 4 17#define R8A7790_CLK_ZT 5 18#define R8A7790_CLK_ZX 6 19#define R8A7790_CLK_ZS 7 20#define R8A7790_CLK_HP 8 21#define R8A7790_CLK_I 9 22#define R8A7790_CLK_B 10 23#define R8A7790_CLK_LB 11 24#define R8A7790_CLK_P 12 25#define R8A7790_CLK_CL 13 26#define R8A7790_CLK_M2 14 27#define R8A7790_CLK_ADSP 15 28#define R8A7790_CLK_IMP 16 29#define R8A7790_CLK_ZB3 17 30#define R8A7790_CLK_ZB3D2 18 31#define R8A7790_CLK_DDR 19 32#define R8A7790_CLK_SDH 20 33#define R8A7790_CLK_SD0 21 34#define R8A7790_CLK_SD1 22 35#define R8A7790_CLK_SD2 23 36#define R8A7790_CLK_SD3 24 37#define R8A7790_CLK_MMC0 25 38#define R8A7790_CLK_MMC1 26 39#define R8A7790_CLK_MP 27 40#define R8A7790_CLK_SSP 28 41#define R8A7790_CLK_SSPRS 29 42#define R8A7790_CLK_QSPI 30 43#define R8A7790_CLK_CP 31 44#define R8A7790_CLK_RCAN 32 45#define R8A7790_CLK_R 33 46#define R8A7790_CLK_OSC 34 47 48#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */ 49